Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2007-05-15
2009-06-23
JeanPierre, Peguy (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S122000
Reexamination Certificate
active
07551114
ABSTRACT:
A stage of a pipelined ADC used as a sub-ADC in a time-interleaved ADC is operated using a first set of clock signals, with a next stage being operated using a second set of clock signals. The first set and second set of clock signals are designed to cause the start of hold phases of the stage to occur earlier than the sample phases of the next stage. In an embodiment, the start of the hold phases is coincident with the end of an immediately preceding sample phase of the stage. As a result, more time is provided for the output of an amplifier used in the stage to settle to a final value, thus permitting use of a low speed amplifier and reduction in power consumption in the interleaved ADC. In an embodiment, the stage corresponds to an earliest stage in the pipelined sub-ADC.
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patent: 4968988 (1990-11-01), Miki et al.
patent: 6323800 (2001-11-01), Chiang
patent: 7053804 (2006-05-01), Nairn
patent: 7075471 (2006-07-01), Gupta
patent: 7170436 (2007-01-01), Ye
Joy Jomy
Seedher Ankit
Shrivastava Ayaskant
Brady W. James
Jean-Pierre Peguy
Shaw Steven A.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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