Reducing metastable-induced errors from a frequency detector...

Details Reducing metastable-induced errors from a frequency detector... Reducing metastable-induced errors from a frequency detector...

2006-08-22

2006-08-22

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C375S375000, C331S025000

Reexamination Certificate

active

07095259

ABSTRACT:
A technique for reducing the likelihood that a frequency detector will incorrectly assert control over a VCO because of metastable-induced errors involves qualifying frequency detector control signals by requiring multiple consecutive control signals that indicate the frequency detector should assert control over the VCO before the frequency detector is allowed to assert control over the VCO. In an embodiment, the frequency detector control signals are qualified by a series of full-swing library cell flip-flops.

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B. Wu, R. Walker, “PLL Design in HP's Gigabit Ethernet Transceiver,” 1997 HP Design Technology Conference Proceedings, pp. 367-375.

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