Reducing memory access in a multi-cache multiprocessing environm

Details Reducing memory access in a multi-cache multiprocessing environm Reducing memory access in a multi-cache multiprocessing environm

1992-12-18

1996-03-26

Lane, Jack A.

395470, 395473, G06F 1208

Patent

active

055028284

ABSTRACT:
A cache control circuit reduces accesses of main memory in a multiple cache multiprocessing system. The circuit allows the use of multiple caches with a single central processing unit, and facilitates burst-mode operations.

REFERENCES:
patent: 4654782 (1987-03-01), Bannai et al.
patent: 5210843 (1993-05-01), Ayers
patent: 5398325 (1995-03-01), Chang et al.
patent: 5404489 (1995-04-01), Woods et al.
IBM Technical Disclosure Bulletin, "Memory Management Mechanism to Reduce Cache-Line Contention", Anonymous, vol. 32, No. 8B, Jan. 1990, pp. 25-26.
Patent Abstracts of Japan, vol. 015, No. 122 (P-1184), Mar. 26, 1991, abstract of Ishida Itsuko et al., "Data Processor", Japanese 03 01-345, Jan. 17, 1991.
Computer Design, Warren Andrews, "New Cache Tags Bring Flexibility, Performance to Memory Subsystems", Jul. 1, 1990, pp. 42-46.
Computer Design, Ron Wilson, "Will the Search for the Ideal Memory Architecture Ever End?", Jul. 1, 1990, pp. 78-90.

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