Static information storage and retrieval – Powering – Conservation of power
Reexamination Certificate
2002-02-05
2003-04-22
Lebentritt, Michael S. (Department: 2824)
Static information storage and retrieval
Powering
Conservation of power
C365S226000
Reexamination Certificate
active
06552949
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to techniques for reducing leakage current in a memory device, and in particular to the reduction of leakage current in a memory device having memory cells coupled to bit lines, in situations where the memory device enters a power down mode of operation.
2. Description of the Prior Art
A memory device will typically comprise a plurality of memory cells arranged in rows and columns. For each column, a pair of bit lines is typically provided which is coupled to the column of memory cells, and in preferred embodiments is used to write data to, and read data from, individual memory cells within that column. Bit line precharge circuitry is typically used to precharge each pair of bit lines to a predetermined voltage level during a precharge phase, with the pair of bit lines being arranged such that, when a particular memory cell in the corresponding column is selected in an evaluate phase following the precharge phase, a relative change in voltage level between the pair of bit lines indicates the data value stored within the selected memory cell.
When a data processing system enters a power down (also referred to as a power saving) mode of operation, certain components may be shut down completely, with the power to those components being removed, whilst other components may enter an inactive state where they are not actively consuming power (e.g. internal nodes are not changing state), but where the power supply is still maintained to the component. This may be appropriate in order to ensure that the state of the component is not lost during the power down mode. A memory device such as a cache would be a typical example of a component which during a power saving mode of operation may still have the power supply provided to it to ensure that the contents of the cache memory do not need to be stored to external memory before the power down mode is entered. If this was not done, and the power supply was removed, the data in the cache would be lost.
However, when a memory device of the above type is subject to a power saving mode where the power supply is still provided to the device, there is a tendency for some leakage current to flow via the bit lines during the power saving mode.
Up to now, the issue of leakage current has typically not been of significant concern in many implementations. However, as components decrease in size, it has been found that leakage current tends to increase. Hence, it would be desirable to develop techniques which enable a reduction in the leakage current when a memory device is placed in a power saving mode of operation. Clearly, this becomes even more desirable when seeking to develop systems which are increasingly more power efficient.
SUMMARY OF THE INVENTION
Viewed from a first aspect, the present invention provides a memory device, comprising: a column of memory cells, each memory cell being arranged to store a data value; a pair of bit lines coupled to said column of memory cells; bit line precharge circuitry for precharging said pair of bit lines to a predetermined voltage level during a precharge phase, the pair of bit lines being arranged such that, when a particular memory cell in said column is selected in an evaluate phase following said precharge phase, a relative change in voltage level between the pair of bit lines indicates the data value stored within the selected memory cell; power down control circuitry arranged when the memory device is to enter a power down mode to prevent the bit line precharge circuitry from precharging said pair of bit lines; and selector circuitry arranged when the memory device is to enter said power down mode to ensure that none of said memory cells in said column are selected.
In accordance with the present invention, a memory device having a column of memory cells, a pair of bit lines coupled to the column of memory cells, and bit line precharge circuitry, is further provided with power down control circuitry arranged, when the memory device is to enter a power down mode of operation, to prevent the bit line precharge circuitry from precharging the pair of bit lines. Further, selector circuitry is arranged when the memory device is to enter the power down mode to ensure that none of the memory cells in the column are selected. By this approach, it is ensured that the bit lines are no longer “strongly” driven to the predetermined voltage level, the use of the term “strongly” in this case being intended to indicate the act of being driven by a “turned-on” device. Hence, in effect, this approach leaves the bit lines floating in the power down mode of operation.
Surprisingly, it has been found that this approach significantly reduces the leakage current that would otherwise flow through the bit lines, and the memory cells coupled to those bit lines. On further analysis, the inventors of this invention have realised that this is due to the fact that a path of significant leakage current is altered by taking the above described steps when entering the power down mode of operation, and that this altered path exhibits a significantly increased resistance to current flow when compared with the unaltered leakage current path observed in typical prior art memory devices.
More particularly, it was found that whereas in the typical prior art memory device, the path of significant leakage current passed through the precharge circuitry, bit lines, and particular components of the memory cell, when the memory device was arranged in accordance with the present invention, the path of significant leakage current instead passed via the bit lines between memory cells in a particular column that are storing different data values. This latter path typically has a significantly increased resistance compared with the above described significant leakage current path of prior art memory devices, which leads to the observed reduction in leakage current.
The power down control circuitry may be arranged in a variety of ways, provided that it serves to prevent the bit line precharge circuitry from precharging the pair of bit lines when the memory device enters the power down mode of operation. However, in one embodiment of the present invention, the power down control circuitry is arranged to receive a power down signal indicating whether the power down mode is set and a precharge signal indicating whether the precharge phase is active, and to generate as its output an input signal to the bit line precharge circuitry, such that when the power down signal indicates that the power down mode is set, the output signal from the power down control circuitry is arranged to cause the bit line precharge circuitry to be turned off.
In such an embodiment, the bit line precharge circuitry preferably comprises one or more P type devices, and said power down control circuitry is arranged to apply a logical OR gate function to the power down signal and the precharge signal. In such an embodiment, the precharge signal will be set to a logic 0 level when the apparatus is in the precharge phase and to a logic 1 level when the apparatus is not in the precharge phase, whilst the power down signal will be set to a logic 1 level when the power down mode is to be entered, and will be set to a logic 0 level otherwise. Accordingly, since the power down control circuitry is arranged to apply a logical OR gate function, it is clear that when the power down signal is set to a logic 1 level, a logic 1 signal will be output by the power down control circuitry to the bit line precharge circuitry, and given that the bit line precharge circuitry comprises one or more P type devices, this will cause the bit line precharge circuitry to be turned off.
In an alternative embodiment, the power down control circuitry is positioned in series with the bit line precharge circuitry between the pair of bit lines and the predetermined voltage level, the power down control circuitry being arranged to receive a power down signal indicating whether the power down mode is set and to turn off when the pow
Brauer Michael Louis
Piejko Arthur R
Silla Mark Allen
Williams, III Gerard Richard
Arm Limited
Lebentritt Michael S.
Nixon & Vanderhye P.C.
Phung Anh
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