Static information storage and retrieval – Interconnection arrangements – Magnetic
Reexamination Certificate
1999-09-28
2001-02-13
Mai, Son (Department: 2818)
Static information storage and retrieval
Interconnection arrangements
Magnetic
C365S063000, C365S206000, C365S214000
Reexamination Certificate
active
06188598
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to reducing the adverse impact of noise coupling in signal lines of, for example, an integrated circuit (IC). In particular, the invention relates to bitline architectures which reduce the impact of noise to improve sensing of memory cells.
BACKGROUND OF THE INVENTION
Referring to
FIG. 1
, a conventional dynamic random access memory cell
101
is shown. The memory cell comprises a cell transistor
110
and a cell capacitor
150
for storing information. A first junction
111
of the transistor is coupled to a bitline
125
, and a second junction
112
is coupled to the capacitor. A gate electrode
113
of the transistor is coupled to a wordline
126
. A reference or constant voltage (V
pl
) can be coupled to a plate of the capacitor. The plate which is coupled to the reference voltage can serve as a common plate in the memory array.
A plurality of cells are arranged in rows and columns, connected by wordlines in the row direction and bitlines in the column direction. The bitlines can be arranged in various types of bitline architectures, such as open, folded, open-folded, diagonal, multi-level, split-level, or split-level diagonal. Multi-level or split-level bitline architectures are described in, for example, Hamada et al., A Split Level Diagonal Bitline Stack Capacitor Cell for 256 Mb DRAMs, IEDM 92-7990, which is herein incorporated by reference for all purposes.
The bitlines are coupled to sense amplifiers to facilitate memory accesses. Typically, a pair of bitlines is coupled to a sense amplifier. The bitline containing the selected memory cell is referred to as the bitline or bitline true and the other is referred to as the reference bitline or bitline complement.
A memory access typically comprises precharging the bitlines to a predefined voltage (e.g., equalization voltage or V
bleq
). A memory cell within a bitline pair is selected after the bitlines are precharged and floated. The memory cell is selected by rendering the transistor of the memory cell conductive, coupling the memory cell's capacitor to the bitline true. Depending on the value stored in the capacitor, the bitline true is pulled above or below V
bleq
. The reference bitline, in the ideal case, remains at V
bleq
. The voltage difference between the reference bitline and bitline true is the differential voltage. A sense amplifier coupled to the bitline pair senses and amplifies the differential voltage, which is indicative of the data stored in the selected memory cell.
An important issue to consider in designing memory ICs is to provide an adequate sensing signal (i.e., differential voltage) to the sense amplifier in order for the data to be read accurately from memory. The differential signal sensed by a sense amplifier, in an ideal situation, depends on the charge sharing between the bitline and the memory cell. The ratio of the bitline capacitance (and the capacitance of the sense amplifier) to the cell capacitance determines the magnitude of the differential signal. However, the voltage on the reference bitline increases or decreases along with the voltage swing on the bitline true due to noise coupling between the bitlines (intra-bitline coupling). This results in a decrease in the magnitude of the differential signal, which is undesirable as this may lead to incorrect evaluation of the data stored in the memory cell.
Noise coupling from neighboring bitline pairs (inter-bitline coupling) can also reduce the signal margin. This sense amplifiers of the array may not be activated simultaneously. This occurs as a result of, for example, different amplification speeds for a “0” and a “1”, difference in the threshold voltage of the various latch transistors, or a skew in the activation of the sense amplifiers in the top and bottom bank in an interleaved arrangement. Coupling noise from a bitline pair whose differential signal is amplified can reduce the differential signal of a neighboring bitline pair whose differential signal has yet to be amplified.
The problems associated with bitline coupling noise become worse as technology migrates to smaller groundrules due to the fact that the fraction bitline-to-bitline capacitance contribution to the total bitline capacitance increases with smaller dimensions.
As evidenced from the foregoing discussion, it is desirable to reduce the impact of coupling noise to avoid degrading or reducing the signal margin of a differential signal.
SUMMARY OF THE INVENTION
The invention relates to reducing the adverse impacts of coupling noise from neighboring signal lines in integrated circuits with multiple signal line levels. In one embodiment, a memory IC comprises a first bitline pair with first and second bitlines on a first bitline level and a second bitline pair with first and second bitline on a second bitline level. The first bitline pair is adjacent to the second bitline pair. The first bitline pair comprises m twists, where m is a whole number≧1. The second bitline pair comprises n twists, where n is a whole number not equal to m. The twists switch the bitline paths of the bitlines within the bitline pair. The twists are located along the bitline pairs to transform coupling noise between the bitline pairs into common mode noise, which does not adversely impact signal margin.
REFERENCES:
patent: 4980860 (1990-12-01), Houston et al.
patent: 5214601 (1993-05-01), Hidaka et al.
patent: 5475643 (1995-12-01), Ohta
patent: 5602773 (1997-02-01), Campbell
patent: 5864181 (1999-01-01), Keeth
patent: 6034879 (2000-03-01), Min et al.
Gruening Ulrike
Mueller Gerhard
Braden Stanton
Infineon Technologies North America Corp.
Mai Son
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