Reducing grain in multi-phase-clocked CCD imagers

Details Reducing grain in multi-phase-clocked CCD imagers Reducing grain in multi-phase-clocked CCD imagers

1983-03-07

1985-03-26

Murray, Richard

Facsimile and static presentation processing

Facsimile

Recording apparatus

H04N 314

Patent

active

045076847

ABSTRACT:
Grain, a fixed pattern noise which is not attributable just to dark current variations in the imager and which persists even in relatively bright images, is reduced in a CCD imager with three-phase-clocked imager register by introducing an offset potential between gate electrodes in the two clocking phases conventionally held at same potential during image integration times. In field transfer type CCD imagers, using field interlace and three-phase imager-register and field-store-register clocking, the offset potential can be made large enough, not only to reduce grain, but to improve field interlace from two-thirds field interlace towards or to perfect field interlace.

REFERENCES:
patent: 4443818 (1984-04-01), Ohba et al.

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