Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2006-08-22
2008-12-30
Le, Vu A (Department: 2824)
Static information storage and retrieval
Floating gate
Particular connection
C365S185180
Reexamination Certificate
active
07471565
ABSTRACT:
A method for programming that biases a selected word line with a programming voltage. An unselected word line on the source side and an unselected word line on the drain side of the selected word line are biased at a pass voltage that is less than the normal pass voltage. These unselected word lines are both located a predetermined distance from the selected word line. The remaining word lines are biased at the normal pass voltage.
REFERENCES:
patent: 5621684 (1997-04-01), Jung
patent: 5677875 (1997-10-01), Yamagata
patent: 5715194 (1998-02-01), Hu
patent: 5917757 (1999-06-01), Lee et al.
patent: 5959892 (1999-09-01), Lin
patent: 5991202 (1999-11-01), Derhacobian
patent: 6061270 (2000-05-01), Choi
patent: 6107658 (2000-08-01), Itoh et al.
patent: 6240016 (2001-05-01), Haddad
patent: 6469933 (2002-10-01), Choi
patent: 6620682 (2003-09-01), Lee
patent: 6657915 (2003-12-01), Seo
patent: 2002/0060926 (2002-05-01), Choi
patent: 2002/0075727 (2002-06-01), Jeong
patent: 2002/0149958 (2002-10-01), Kunikiyo
patent: 2005/0265097 (2005-12-01), Tanaka et al.
patent: 2006/0002167 (2006-01-01), Rudeck et al.
patent: 2006/0023502 (2006-02-01), Cernea et al.
patent: 2007/0047314 (2007-03-01), Goda et al.
patent: 2007/0236992 (2007-10-01), Oowada
patent: 2007/0258286 (2007-11-01), Higashitani
T. Jung et al., “A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications” IEEE Journal of Solid-State Circuits, IEEE Inc., New York, NY, U.S., vol. 31, No. 11, Nov. 1996, pp. 1575-1583.
K. Suh et al., “A 3.3 V 32 Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme” IEEE Journal of Solid-State Circuits, IEEE Inc., New York, NY, vol. 30, No. 11, Nov. 1995, pp. 1149-1156.
Le Vu A
Leffert Jay & Polglaze P.A.
Micro)n Technology, Inc.
LandOfFree
Reducing effects of program disturb in a memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Reducing effects of program disturb in a memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Reducing effects of program disturb in a memory device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4049591