Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
1999-03-04
2001-04-10
JeanPierre, Peguy (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S144000
Reexamination Certificate
active
06215432
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to integrated circuits comprising a digital logic and sampled analog circuits, and more specifically to a method and apparatus for reducing digital switching noise in such circuits.
BACKGROUND ART
With the advances in integrated circuit technology, it is becoming practical to include increasingly more functionality into single integrated circuit devices. This includes a trend to combine high-precision analog circuitry on the same die as high performance digital circuitry. However, due to the nature of IC design, high-precision analog circuitry can be adversely affected by the noise generated when switching the digital logic. For example, separate power supplies are typically employed to power the digital circuitry and the analog circuits. Noise associated with ground plane coupling between the power supplies will interfere with proper operation of the analog circuitry.
The majority of high-precision analog converters used in such applications are of a kind known as sampled converters. These converters are “sampled” in the sense that their inputs (or outputs) are present only at discrete points in time. This is compared too continuous analog systems in which the input (or output) is continuously available. The presence of digital noise in a sampled analog system can reduce its dynamic range by many dB, thus degrading performance to such an extent that its application in a mixed-signal device may not by viable.
Digital switching noise can be generated from many sources. One major source of noise is due to digital bus output switching, where many outputs of the device switch at the same time. Due to the currents and loads involved in output pads, this generates a relatively large amount of noise compared to purely internal digital circuitry. However, with large synchronous systems where many internal nodes are switching simultaneously, internal noise may also be a problem.
Consider a codec with a peripheral component interchange (PCI) interface, for example. A large part of the digital noise in such a chip will occur due to switching of the PCI outputs during a read transaction (i.e. data output operation). These outputs will toggle after a rising edge of a PCI clocking signal (with a maximum delay of 11 nS). If the toggling of the PCI outputs coincides with an analog sample (for example), the conversion may suffer noise artifacts from the PCI switching. As the sample clock and the PCI clock are completely asynchronous, it is very likely that this will occur during device operation.
What is needed is a method and apparatus for operating mixed-signal devices in such a way that eliminates (or at least keeps to a minimum) the adverse effects of digital noise during sampling by the analog circuitry.
SUMMARY OF THE INVENTION
In a mixed signal IC, conversion between analog and digital signals comprises producing a sample-enable signal based on a system clock. A warning signal, also based on the system clock, is asserted prior to the sample-enable signal. The warning signal is then synchronized with respect to a second clock, which serves as a clocking signal for the digital circuitry portion of the mixed signal IC. The warning signal is coupled to the digital circuitry and serves to momentarily disable the digital circuitry, thus enabling the analog circuitry to operate in the absence of digitally produced noise. When the warning signal is de-asserted, operation of the digital circuitry resumes. In one embodiment of the invention, the digital circuitry is a PCI bus interface circuit.
REFERENCES:
patent: 4746899 (1988-05-01), Swanson et al.
patent: 5010347 (1991-04-01), Yukawa
patent: 5373293 (1994-12-01), Hirata
patent: 5604500 (1997-02-01), Murakami
patent: 5648778 (1997-07-01), Linz et al.
patent: 5757302 (1998-05-01), Hino
patent: 5914681 (1999-06-01), Rundel
patent: 2195848A (1998-04-01), None
Blalack, T. et al., “TP 11.8: The Effects of Switching Noise on an Oversampling A/D Converter,” 1995 IEEE International Solid-State Circuits Conference, U.S., IEEE Inc., New York, vol. 38, pp. 200-201, 367 (Feb. 1, 1995).
Atmel Corporation
Jean-Pierre Peguy
McGuire, Jr. John P.
Schneck Thomas
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