Reducing clock skew in large-scale integrated circuits

Details Reducing clock skew in large-scale integrated circuits Reducing clock skew in large-scale integrated circuits

1991-10-08

1993-08-10

Trans, Vincent N.

Boots, shoes, and leggings

364488, G06F 1560

Patent

active

052355217

ABSTRACT:
In a system of digital chips, the time delay in all clock trees is equalized by equalizing the delay through each level of all trees. The level delays are equalized by adjusting the capacitance of terminators in each net at each level, and/or by adjusting the performance (power) of each driver at each level. Where the capacitance of a net is too low to be compensated by a driver, a capacitive terminator is selectively added to that net.

REFERENCES:
patent: 4263651 (1981-04-01), Donath et al.
patent: 4694403 (1987-09-01), Nomura
patent: 4698760 (1987-10-01), Lembach et al.
patent: 4823278 (1989-04-01), Kikuchi et al.
patent: 4924430 (1990-05-01), Zasio et al.
patent: 5003487 (1991-03-01), Drumm et al.
patent: 5010493 (1991-04-01), Matsumoto et al.
patent: 5077676 (1991-12-01), Johnson et al.
IEEE, 1983 "Timing Analysis for nMOS VLSI", Norman P. Jouppi.
IEEE, 1983 "Signal Delay in RC Tree Networks", Jorge Rubinstein.
IEEE, 1982 "Synchronous Path Analysis in MOS Circuit Simulator", V Agrawal. 1984 Conf on Advanced Research in VLSI M.I.T. Signal Delay in General RC Networks with Application to Timing Simulation of Digital Integrated Circuits.

Affiliated with

Also associated with

Rating

Reducing clock skew in large-scale integrated circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Reducing clock skew in large-scale integrated circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Reducing clock skew in large-scale integrated circuits will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1730838