Reducing clock skew in large-scale integrated circuits

Details Reducing clock skew in large-scale integrated circuits Reducing clock skew in large-scale integrated circuits

1990-03-30

1991-12-31

Lall, Parshotam S.

Boots, shoes, and leggings

364488, G06F 1560

Patent

active

050776762

ABSTRACT:
In a system of digital chips, the time delay in all clock trees is equalized by equalizing the delay through each level of all trees. The level delays are equalized by adjusting the capacitance of terminators in each net at each level, and/or by adjusting the performance (power) of each driver at each level. Where the capacitance of a net is too low to be compensated by a driver, a capacitive terminator is selectively added to that net.

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"Timing Analysis for nMOS VLSI" by N. P. Jouppi, 1983 IEEE 20th Design Automation Conferences, pp. 411-418.
"Signal Delay in RC Tree Networks" by J. Rubinstein et al., IEEE Trans. on Computer-Aided Design, vol. CAD-2, No. 3, Jul. 1983; pp. 202-210.
"Synchronous Path Analysis in MOS Circuit Simulator" by V. D. Agrawal, 1982 IEEE 19th Design Automation Conf., pp. 629-635.
"Signal Delay in General RC Networks . . . Digital Integrated Circuits" by T. Lin et al., 1984 Conf. on Advanced Research in VLSI, M.I.T.

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