Reducing bipolar parasitic effects in IGFET devices

Details Reducing bipolar parasitic effects in IGFET devices Reducing bipolar parasitic effects in IGFET devices

1982-06-30

1989-01-10

Larkins, William D.

Fishing, trapping, and vermin destroying

357 12, 357 13, 357 231, 357 86, 437 34, 437 57, H01L 2704, H01L 2978

Patent

active

047977248

ABSTRACT:
An IGFET is presented which includes a relatively low resistance path across the source-substrate junction to prevent parasitic bipolar effects while maintaining high component density in integrated circuits. The low resistance path across the source-substrate junction is formed by various methods including damaging the crystal structure at the junction interface, supplementing the damaged junction with a heavily doped region underlying the source region and spiking metallurgy. A particular application of the invention allows the prevention of latchup in CMOS devices. The invention also allows the source region of an IGFET to serve the dual functions of a source for a MOSFET as well as an ohmic contact to the underlying well or substrate.

REFERENCES:
patent: 3641403 (1972-02-01), Nakata
patent: 3955210 (1976-05-01), Bhatia et al.
patent: 4035826 (1977-07-01), Morton et al.
patent: 4167747 (1979-09-01), Satou et al.
patent: 4173767 (1979-11-01), Stevenson
patent: 4271424 (1981-06-01), Inayoshi et al.
"Elimination of Latchup in Bulk CMOS", R. S. Payne, W. N. Grant and W. J. Bertram, pp. 248-251.

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