Data processing: generic control systems or specific application – Specific application – apparatus or process – Product assembly or manufacturing
Reexamination Certificate
2002-04-15
2004-09-21
Pert, Evan (Department: 2829)
Data processing: generic control systems or specific application
Specific application, apparatus or process
Product assembly or manufacturing
Reexamination Certificate
active
06795747
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to semiconductor processing for integrated circuits. In one aspect, the present invention relates to reducing error in layer-to-layer overlay alignment. In another aspect, the invention relates to registration methods for asymmetrically deposited films, and more specifically, methods for reducing asymmetrically deposited film induced registration measurement error.
BACKGROUND OF THE INVENTION
Integrated circuits (IC's) are formed by sequentially creating layers on an integrated circuit substrate, such as a semiconductor substrate. These layers can include: insulating layers, polysilicon layers, and conducting layers, such as silicide or metal layers. The layers can be patterned or etched to form IC parts or features (e.g., electronic components, interconnections and the like).
For an IC to operate properly, structures within overlying layers must properly align with one another. However, as integrated circuits become more dense and complex, it is becoming increasingly difficult to achieve registration of overlying structures. Misalignment between the layers can be a limiting factor in achieving increased IC integration density and a functioning device.
Generally, registration of one patterned layer with another can be achieved using special registration marks that are designed into each layer. When the registration marks of one patterned layer are registered with those of a previously patterned layer, it can be assumed that the remainder of the patterned layer is also properly registered with that of the previously-patterned layer.
Monitoring and adjustment of the alignment process was originally performed by human operators using a microscope. The decreasing size of integrated circuit features and layers, and the increasing number of layers per wafer, have contributed to the development of automated alignment processes using specialized tools known in the art. Such tools, including but not limited to: proximity printers, projection printers, aligners and steppers, generally provide systems, methods and computer program products for aligning a pattern with respect to underlying or previous patterns, and/or to the underlying substrate. Such exposure tools (also called a “patterning tool”) are described in greater detail, for example, in U.S. Pat. No. 6,064,486, the disclosure of which is incorporated by reference herein.
The registration mark(s) (also referred to herein as “overlay mark(s)” and “registration measurement structures”) may not be symmetrical, however, thus making it more difficult to find the center position of the registration mark. Moreover, even if the registration mark is symmetrical, subsequent processing can create an asymmetric coating that can include one or more additional layers on or adjacent to the registration mark. Asymmetry in such a coating, or in the mark itself, can result in an asymmetric registration signal that can cause registration of a patterned structure to be measured or perceived incorrectly.
If the registration structure comprises a raised feature or component (e.g., a mesa) or a depressed feature or component (e.g. a trench) on an integrated circuit substrate, one or more material layers may be formed onto the feature. Such layers can be formed asymmetrically over the feature due to the topography of the feature (e.g., raised or depressed), itself and/or due to asymmetries in the film or coating forming process. For example, metal deposition and photoresist film or coatings processes can produce asymmetries over the surface of a substrate. Such asymmetric films can make it difficult to accurately define the centerline of the registration mark, and thus, induce an asymmetric film registration error that can cause misalignment between consecutive layers of an IC.
Deposition processes are referred to as “metal deposition processes” when the material layer being deposited is a metallic material. Sputtering of a metal onto a silicon wafer is one specific example of an “asymmetric deposition process”. Sputtering techniques (also known as physical vapor deposition or “PVD”) are well known in the art. See Wolf and Tauber,
Silicon Processing for the VLSI Era
, Vol. 1, Chpt. 11, (Lattice Press 2000); Zant,
Microchip Fabrication
, pp. 411-16 (McGraw-Hill 2000); and Aronson, “Fundamentals of Sputtering”,
Microelectronics Manufacturing and Testing
, January 1987. Examples of conventional sputtering techniques include high density plasma (HDP) or collimated sputtering. Another exemplary conventional sputtering process is the sputtering of aluminum for metal interconnects.
Attempts have been made to reduce and/or eliminate registration error caused by asymmetrically deposited films. For example, one solution has included an attempt to develop distinctive overlay marks, such as “chopped overlay marks”. However, while such overlay marks can work to affect the way asymmetric films are deposited, current registration tools and associated methods for their use have heretofore been unable to appropriately obtain accurate registration data. This has been the case for a variety of reasons, one of which is that the metal film that is deposited on registration marks can appear opaque to a broadband light of the kind typically used in current registration tools.
Accordingly, it would be desirable to provide methods, apparatuses and systems for reducing asymmetric film induced registration error in the semiconductor industry.
SUMMARY OF THE INVENTION
The present invention relates generally to semiconductor fabrication techniques and, more particularly, to the reduction, and potentially the elimination, of asymmetric film induced registration error is disclosed herein. The method, apparatuses, and systems disclosed herein ideally solve the aforementioned problems and reduce such false overlay error in a cost-effective manner.
In one aspect, the invention provides methods for reducing registration measurement error due to an asymmetrically deposited film using critical dimensions. The method employs a registration measurement structure formed in overlying upper and lower layers of a semiconductor construction, the lower layer comprising a first component of the registration measurement structure, and the upper layer comprising a second component of the registration measurement structure, the first component comprising a first edge and a second edge, and a first distance from the first edge to the second edge, and the second component comprising a first edge and a second edge. An exemplary registration structure comprises a box-in-box registration structure. One hallmark of the method is that critical dimensions of an overlay structure can be determined, and using the critical dimension determinations in conjunction with overlay measurements, registration error can be substantially reduced, and potentially eliminated.
In one embodiment of the method, the method comprises acquiring data from the first component of the registration measurement structure to provide a first critical distance value from the first edge to the second edge; acquiring data from the position of the first component in relation to the second component to provide an apparent registration measurement; acquiring data from the first component having an asymmetrical film layer deposited thereon, to provide a second critical distance value from the first edge of the first component to an edge of the film layer disposed contiguously to the first edge of the first component; comparing the second distance value to the first distance value to generate an alignment error value corresponding to a third distance value measured from said edge of the film layer to the second edge of the first component; comparing the apparent registration measurement and the third distance value to remove the alignment error and generate an actual registration value; and conveying the actual registration value to a patterning apparatus for aligning a subsequent layer to the structure.
In another embodiment, the method comprises determining a first critic
Bowes Steve W.
Byers Erik
Harrison Monica D.
Micro)n Technology, Inc.
Pert Evan
Whyte Hirschboeck Dudek SC
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