Reduced voltage swing digital differential driver

Details Reduced voltage swing digital differential driver Reduced voltage swing digital differential driver

2002-05-30

2003-05-27

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Current driver

C327S563000, C327S065000, C327S206000, C326S083000

Reexamination Certificate

active

06570415

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to predrivers, and, more particularly, to a reduced voltage swing digital differential driver.
BACKGROUND OF THE INVENTION
Predrivers drive the inputs of a differential comparator to a specified level. Conventional predrivers include an inverter connected to a p-type MOS transistor and a n-type MOS transistor. The gates of the p-type and n-type MOS transistors connect to each other and to the inverter. The drains of the p-type and n-type MOS transistors connect to each other respectively to form an output. The source of the p-type MOS transistor connects to the power supply rail while the source of the n-type MOS transistor connects to ground. In operation when the input represents a high voltage or a ‘1’, the p-type MOS transistor switches on and current flows from the power supply rail through the p-type MOS transistor to pull the output node of the predriver high. When the input represents a low voltage or a ‘0’, the n-type MOS transistor switches on and current flows through the n-type MOS transistor to ground, pulling the output node of the predriver low.
Since the signals sent to the input are digital, the voltage at the output swings from ground to the full power supply voltage level. As a result, the switching speed is slow and high current or power consumption exist.
There, however, exists a need for a predriver that has faster switching speed and low current or power consumption.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of predrivers, the present invention teaches a predriver circuit for a differential comparator having a first and second power supply rail. The predriver circuit, having an input and an output, includes an inverter connected to the input and a p-type MOS transistor having a drain, a source and a gate, whereby the source is coupled to the first power supply rail and the gate is coupled to the inverter. A first n-type MOS transistor, having a drain, source and a gate, couples to the p-type MOS transistor. The gate of the n-type MOS transistor couples to the gate of the p-type MOS transistor. The drain of the first n-type MOS transistor couples to the drain of the p-type MOS transistor to form an output. A second n-type MOS transistor, having a drain, a source, and a gate, couples to the first n-type MOS transistor. The drain of the second n-type MOS transistor couples to the source of the first n-type MOS transistor. The source of the second n-type MOS transistor couples to ground. The gate of the second n-type MOS transistor couples to the output. The presence of the second n-type MOS transistor alters the voltage swing of the predriver to be from the threshold voltage level to the full power supply voltage as oppose to from ground to the full power supply voltage which substantially reduces current or power consumption.
Advantages of this design include but are not limited to an predriver having a high performance, simple, and cost effective design.


REFERENCES:
patent: 4571504 (1986-02-01), Iwamoto et al.
patent: 5429442 (1995-07-01), Schrader
patent: 5973526 (1999-10-01), Dabral
patent: 6130562 (2000-10-01), Bosch et al.
patent: 6198307 (2001-03-01), Garlepp et al.
patent: 6433602 (2002-08-01), Lall et al.

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