Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1998-02-11
2001-05-29
Brown, Glenn W. (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S765010
Reexamination Certificate
active
06239609
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to testing of semiconductor devices, and more particularly to a method for reducing transistor leakage currents in integrated circuits to improve the accuracy of quiescent current testing.
2. Description of the Related Art
Integrated circuits (ICs) have become key components of many consumer and commercial electronic products, often replacing discrete components and enhancing product functionality. The semiconductor processing technologies that produce these integrated circuits have advanced to the point where complete systems can often be reduced to a single integrated circuit. These integrated circuits (also referred to as “chips”) may use many functions that previously could not be implemented together on a single chip, including: microprocessors, digital signal processors, mixed signal and analog functions, large blocks of memory and high speed interfaces. It is a common practice for the manufacturers of such integrated circuits to thoroughly test device functionality at the manufacturing site. However, the complex nature of today's integrated circuits presents new testing challenges. Continually shrinking device geometries, coupled with the high cost of operating semiconductor processing equipment, result in increased demands on integrated circuit suppliers to improve process yields and develop new test strategies.
Currently, complementary metal-oxide-semiconductor (CMOS) is the most popular technology for fabricating integrated circuits due to its inherent low power consumption in high density designs. CMOS circuits use complementary p-channel metal-oxide-semiconductor field-effect (PMOS) transistors and n-channel metal-oxide-semiconductor field-effect (NMOS) transistors to produce fully static designs that ideally consume no power except when switching states. In practice, however, CMOS circuits draw low leakage or quiescent currents—also referred to as quiescent power supply current or IDDQ—in a static state. Testing the amount of quiescent current consumed by an integrated circuit provides a relatively simple and cost effective test strategy for screening for physical defects, many of which cause a measurable increase in quiescent current consumption.
The main goal of semiconductor test strategies is to screen out devices having functional or physical defects, while establishing test limits that do not reject good devices. Many test development strategies have evolved, and often combinations of these strategies are utilized to provide a high degree of fault coverage. Test development strategies include functional tests wherein automatic test equipment (ATE) test programs are performed in which the circuit under test is stimulated with specified inputs while the outputs are monitored to determine if they correspond with simulated logic values. Structural tests are also utilized and rely on a model of logical circuit faults. These tests are often implemented using “boundary scan” or “full scan” circuitry in conjunction with structural test sets. Structural tests sometimes begin with functional logic simulations that have been fault graded and enhanced for higher fault coverage.
Another test development strategy, physical defect testing, involves creating specific tests designed to detect possible real physical defects that can occur in a circuit. Physical testing is useful for detecting defects that may not cause the device to fail functional or structural testing, but may lead to failure in the field. Defects in integrated circuits take many forms, some of which are test pattern sensitive. Gate oxide defects, drain to source current leaks (punch-through), and p-n junction current leaks (such as drain or source to diffusion current leaks) tend to be pattern sensitive, while resistive shorts to ground or the power supply voltage are usually pattern insensitive. In either case, quiescent current tests are a valuable tool in detecting faults.
Generally, the result of test development is an ATE test program or test “set” providing stimulus/response test “vectors” in the language of the ATE. The ATE test set causes the inputs of the device under test to be driven in a predetermined manner, while output pin voltages are compared to stored test values. The ATE test set is derived mainly from functional and structural test development logic simulations.
When testing quiescent current with a functional test set, the tester is typically halted at predetermined test steps suitable for quiescent current testing. Once halted (i.e., no transistor state switching is occurring) the power supply or quiescent current of the device under test is measured by the ATE and the resulting value is compared to predetermined reference values or test limits. Such quiescent current tests are effective in detecting many faults not recognized by other test strategies.
For example, with most functional tests that measure voltage, faults must propagate to the output pins of the device under test for the ATE to differentiate between a good or bad device. Quiescent current tests differ in that current is sensed rather than voltage, providing a simple means to monitor the entire circuit or portions thereof for overcurrent conditions. The quiescent current measurements are typically accomplished via the tester's parametric unit.
Accurate quiescent current testing requires that the device under test be in a static DC condition, with any circuitry that draws current in the static DC condition being disabled or accounted for in the test limits. Preferably analog circuitry, input/output pads, and other circuitry not conducive to quiescent current testing are provided with separate, dedicated power supply inputs, so that digital core circuitry can be tested separately.
Although quiescent current testing is performed by the majority of semiconductor manufacturers, no standardized method exists for selecting the quiescent current reference values or limits that determine whether a device passes or fails the test. Test limits are often quite loose and sometimes established on an arbitrary basis, frequently ranging between ten microamps to over one milliamp. One method for setting test limits involves simply estimating the number of transistors in a device and multiplying by a conversion factor. In another method, representative devices are sampled to arrive at acceptable threshold limits. All of these prior methods for establishing quiescent current test limits suffer from inherent inaccuracies. If the quiescent current test limits are set too low, good devices may be rejected. If the quiescent current test limits are set too high, faulty devices may escape detection. Presently, no significant attempt is made to minimize the effects of inherent and expected quiescent currents other than placing the device under test in a static DC state.
SUMMARY OF THE INVENTION
Briefly, the present invention provides a method for improving the accuracy of quiescent current testing by reducing the effects of inherent transistor leakage currents. Quiescent current tests are performed at a number of different supply voltages, with the acceptability of the device under test being partially dependent on the non-linearity of the resulting measurements, thereby minimizing reliance on absolute quiescent current test limits.
Initially, the device under test is placed into a static DC state in a traditional manner. Quiescent current is then measured with the power supply to the device set to a nominal operating voltage. Next, a fixed voltage lower than the nominal power supply voltage is applied to the integrated circuit in order to reduce the quiescent current consumed by its transistors. An additional quiescent current measurement is then taken.
The difference in quiescent current between the first and second measurements is then calculated. Additional quiescent current measurement(s) are also taken at increasingly lower supply voltages. The differences in quiescent currents between each of these measurements are calculated. After a sufficient number o
Chan Victer K.
Sugasawara Emery O.
Vasishta Ronnie V.
Brown Glenn W.
LSI Logic Corporation
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