Reduced-voltage NMOS output driver

Details Reduced-voltage NMOS output driver Reduced-voltage NMOS output driver

1992-07-01

1994-01-25

Hudspeth, David R.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307448, 307451, H03K 19003

Patent

active

052818691

ABSTRACT:
A tri-state output buffer circuit employs N-channel pull-up and pull-down transistors, with another N-channel transistor connected between the pull-up and pull-down transistors and having its gate connected to the low-voltage supply. An output node at one side of the pull-up transistor may be driven to a voltage higher than the supply, without subjecting the pull-up to hot-carrier effects or other deleterious effects of over-voltage. When in the high-impedance output state, the gate of the pull-up is shorted to an intermediate node which is the drain of the pull-down transistor, using a P-channel and an N-channel transistor responsive to the logic input. The voltage on the gate of the pull-up transistor is allowed to track the output up to the reduced voltage supply minus V.sub.TN when in the high-impedance state, by tying the gate of the pull-up transistor to the intermediate node; this prevents damage to the pull-up due to hot-carrier effects.

REFERENCES:
patent: 3839646 (1974-10-01), Soloway
patent: 4275313 (1981-06-01), Boll et al.
patent: 4345172 (1982-08-01), Kobayashi et al.
patent: 4347447 (1982-08-01), Proebsting
patent: 4782250 (1986-11-01), Adams et al.
patent: 4825106 (1989-04-01), Tipon et al.
patent: 4963766 (1990-10-01), Lundberg
patent: 5160855 (1992-11-01), Dobberpuhl
patent: 5172016 (1992-12-01), Dobberpuhl

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