Reduced video signal processing circuit

Details Reduced video signal processing circuit Reduced video signal processing circuit

1996-10-15

1999-12-28

Lee, Michael H.

Television

Format conversion

Conversion between standards with different aspect ratios

348565, 348567, 348473, 348581, H04N 7081

Patent

active

060088540

ABSTRACT:
An input processing section reduces the content of an input video signal according to reduction ratio data, and the reduced video signal is stored in field memories. A display processing section reads a reduced video signal from the field memories to execute window display processing thereto according to video size SIZ data and video position data (X, Y). In this event, an input video clock generator, controlling a writing operation to the field memories, computes video size SIZ data from the reduction ratio data, and writes the SIZ data as a header, along with the reduced video signal, into the field memories via the input processing section. The SIZ data is read to be output to the display processing section and a display video clock generator for controlling reading.

REFERENCES:
patent: 5270831 (1993-12-01), Parulski et al.
patent: 5402187 (1995-03-01), Ezaki
patent: 5455631 (1995-10-01), Nakajima
patent: 5557336 (1996-09-01), Nakajima
patent: 5638485 (1997-06-01), Kobayashi

Affiliated with

Also associated with

Rating

Reduced video signal processing circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Reduced video signal processing circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Reduced video signal processing circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2385967