Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit
Reexamination Certificate
2000-06-23
2002-10-08
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Particular stable state circuit
C327S210000, C327S211000
Reexamination Certificate
active
06462596
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to logic circuits, and more particularly to static flip-flops which trigger on both the rising and falling edges of a clock signal.
2. Background Description
In order to reduce the complexity of circuit design, a large proportion of digital circuits are synchronous circuits; that is, they operate based on a clock signal. Among the more popular synchronous digital circuits are edge-triggered flip-flops. These flip-flops are desirable, especially in digital memories, registers, and caches, because they simplify circuit design, for example, by requiring stability of input data only during short intervals of time.
Edge-triggered flip-flop circuits may be classified into one of two types. The first type latches data on either the rising edge or falling edge of a clock signal. While these so-called single-edge-triggered (SET) flip-flops are in common use today, they are not without drawbacks. From a functional standpoint, they tend to be inefficient. For example, because latching occurs on only one of the rising and falling edges of a clock signal, data flow tends to be slow, i.e., at only one half the clock edge frequency. Also, because of their single clock-edge operation, SET flip-flops incur the power cost of operating at two clock edges per interval while using only one of the edges.
The second type of edge-triggered flip-flop operates on both the rising and falling edges of a clock signal. For a given clock signal, these so-called double-edge-triggered (DET) flip-flops are faster (i.e., operate at higher frequencies) than SET flip-flops, and consume about the same power as the SET flip flops. DET flip-flops are themselves classified into types: dynamic and static. In a dynamic DET flip-flop, latched data is lost if the clock is slowed down below a certain level. On the other hand, in a static DET flip-flop, latched data is retained indefinitely. Thus, static DET flip-flops are preferable for rugged (e.g., variable clock tolerant) digital memory design.
Some DET flip-flops are disclosed in the article by S. H. Unger entitled “Double edge-triggered flip-flops,” IEEE Trans. Computer, Vol. C-30, No. 6, pp. 447-451, June 1981. While the flip-flops described in this article are faster compared with some SET flip-flops, their complex design (e.g., a large number of circuit elements) has made it undesirable. In his work, Unger presents DET designs wherein the ones with simplest logic complexity required delay elements which reduce allowable operating speeds. The other designs are between 50% and 100% more complex, in terms of components required, than the corresponding SET circuits. In contrast, the present invention (to be described below) is not based on delay elements. Instead, the present invention uses parallel latching on rising and falling clock edges which cater to maximum operating speeds. Furthermore, the design of the present invention is less complex in terms of components required than all the designs of Unger.
Various attempts have been made to reduce the complexity of DET-type flip flop circuits. See, for example, “A Novel CMOS Implementation of Double-Edge-Triggered Flip-Flops,” IEEE Journal of Solid-State Circuits, Vol. 25, No. 4, pages 1008-1010, August 1990, by S. Lu and M. Ercegovac; “Double-Edge-Triggered D-Flip-Flops for High-Speed CMOS Circuits,” IEEE Journal of Solid-State Circuits, Vol. 26, No. 8, pages 1168-1170, August 1991, by M. Afghahi and J. Yuan; “Reduced Implementation of D-Type DET Flip-Flops,” IEEE Journal of Solid-State Circuits, Vol. 28, No. 3, pages 400-402, March 1993, by Gago et al.; “Low Power Design using Double Edge Triggered Flip-Flops,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 2, No. 2, pages 261-265, June 1994, by Hossain et al.; “High-performance two-phase micropipeline building blocks: double-edge-triggered latches and burst-mode select and toggle circuits,” IEE Proc.—Circuits Devices Systems, Vol. 143, No. 5, pages 282-288, October 1996, by Yun et al.; and “Low-power double-edge triggered flip flop,” Electronics Letters, Vol. 33, No. 10, pages 845-847, May 1997, by Blair. See also U.S. Pat. Nos. 5,179,295, 5,250,858, and 5,793,236.
In this work, Lu et al. present a static DET flip flop design. They present a CMOS implementation that requires 26 MOS transistors with increased complexity vis a vis Unger, whose fast DET D flip flop they characterize as requiring 36 transistors for CMOS implementation with local clock inversion. Lu's design has two loops for maintaining charge levels as a static flip flop that does not depend on the clock period. One loop exists in a high clock enabled latch and the other loop exists in a low clock enabled latch. In an enabled latch's loop, the enablement being decided by the clock, the feedback of data occurs via an inverter. The loops are isolated from each other. There is not sharing of paths among the loops.
Afghahi et al.'s design is for a dynamic DET flip flop. The design is not for a static DET flip flop. The circuits require 20 transistors for a CMOS implementation which does not require an inverted clock.
Yun et al.'s design comprises a psuedo-static version of Afghahi's dynamic design. The design is not that of a static flip flop and requires more transistors than Afghahi's design.
Gago et al. provide a static DET design and a dynamic DET design. They provide an 18 transistor CMOS implementation of the static design in which both Q and Q′ terminals are provided (16 transistor, if Q′ is not to be provided) and the availability of an inverted clock line is assumed. The design requires two more transistors if the clock is to be inverted locally. The design comprises two latches, each of which has a loop within itself for maintaining charge levels for providing static functionality. The feedback path in each loop is designed to be weak in comparison to the forward path and is based on inverting output data. The loops are isolated from each other except for sharing a common terminal, Q, which is also one of the outputs of the flip flop. There is no shared path among the loops, with distinct input and output nodes for the path.
Hossain et al. provide a static DET design and a dynamic DET design. This includes a 16 transistor CMOS implementation of the static design in which the availability of an inverted clock is assumed. The design requires two more transistors if the clock is to be inverted locally. The design also comprises two latches, each of which has a loop within itself for maintaining charge levels for providing static functionality. The feedback path in each loop includes an inverter and is switched by the clock. The loops are also isolated from each other.
Blair provides a static DET design and a semi-static DET design. The static DET design is a modified version of Hossain's static design, in which the feedback path in the loop within a latch is modified to be an unswitched, permanently ON, weak path. The loops of the latches are isolated from each other. A third loop is formed by feeding back the Q terminal to a Q′ terminal using a weak PMOS pull-up transistor. The pull-up transistor acts as a weak inverter when Q is low and in this case, pulls Q′ to high. When Q is high, the pull-up transistor is disabled. In order to reduce switching capacitance of the weak inverters in the loops within the latches, Blair describes an implementation of the inverters using “minimum area” transistors in series with permanently ON weak transistors. Using such weak inverters, the number of transistors needed for the static CMOS implementation described is 19. This assumes that an inverted clock is available, without which, the number of transistors is increased by two.
Varma et al. provide a static DET design and a dynamic DET design. This includes a 16 transistor CMOS implementation of the static design in which the availability of an inverted clock is assumed. The design requires two more transistors if the clock is to be inv
Coca T. Rao
Lam Tuan T.
Whitham Curtis & Christofferson, P.C.
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