Reduced static phase error CMOS PLL charge pump

Details Reduced static phase error CMOS PLL charge pump Reduced static phase error CMOS PLL charge pump

2001-05-04

2002-10-15

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C327S157000

Reexamination Certificate

active

06466078

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method and/or architecture for implementing phase lock loop (PLL) charge pumps generally and, more particularly, to a method and/or architecture for implementing reduced static phase error CMOS PLL charge pumps.
BACKGROUND OF THE INVENTION
FIG. 1
shows a circuit
10
implementing a conventional PLL. The circuit
10
includes a circuit
12
, a circuit
14
, a circuit
16
, a circuit
18
and a circuit
20
. The circuit
12
is implemented as a phase frequency detector (PFD), the circuit
14
is implemented as a voltage controlled oscillator (VCO), the circuit
16
is implemented as a passive loop filter, the circuit
18
is implemented as a current source and the circuit
20
is implemented as a current source. The PFD
12
receives a reference signal REF and a feedback signal FB from the VCO
14
. The PFD
12
generates a pump up signal (UP) or a pump down signal (DN). The circuits
18
and
20
respond to the pump up signal UP and the pump down signal DN to generate currents IUP and IDN. The currents IUP and IDN present charge to the passive loop filter to generate a control voltage VCTRL.
The PLL
10
attempts to match the phase and frequency of the feedback signal FB and the reference signal REF with a negative feedback loop. The PFD
12
senses the phase/frequency error between the signal REF and the signal FB, generating the signals UP and DN with pulse widths proportional to the error.
The PLL charge pump
10
asserts fixed source current (IUP) and sink current (IDN) on the loop filter for the duration of the UP (i.e., TUP) and DN (i.e., TDN) pulse widths, respectively. The application of current on the loop filter
16
modulates the control voltage VCTRL of the PLL voltage controlled oscillator
14
. The change in the control voltage VCTRL raises/lowers the frequency and phase of the output OUT of the VCO
14
, which is then fed back to the PFD
12
as the signal FB. Therefore, the PLL
10
operates as a control loop that attempts to match the phase and frequency of the VCO
14
to that of an external reference signal REF.
As the PLL
10
achieves phase lock (i.e., the signal OUT=REF), the pulse widths of the signals UP and DN become equal indicating no phase error between the signals OUT and REF. With the pulses UP and DN equal, current sourced to the loop filter
16
is equal to the current sunk, resulting in zero net charge being delivered. The zero net charge freezes the control voltage VCTRL, on the loop filter
16
and holds the phase and frequency of the output OUT of the VCO
14
. Ideally, when the PLL
10
is in lock, the signals REF and OUT match in both phase and frequency. However, if the phase error between the signal REF and the signal FB were sensed incorrectly, the PLL
10
would lock the signal OUT to the signal REF with the same error.
Since the PFD
12
is responsible for sensing the phase error in the PLL
10
, an error in the PFD
12
would lead to phase error in the PLL
10
. However, the magnitude of the phase error detected by the PFD
12
must also be translated into a proportional net charge delivered to the loop filter
16
by the charge pump (i.e., the circuits
18
and
20
). As previously stated, the net charge delivered by the charge pump is dependent on the fixed source/sink currents and the durations of the pulses UP and DN (QNET=IUP*TUP−IDN*TDN). If there is either a mismatch in the fixed currents or a skew in the duration of the pulses UP/DN, a non-zero net charge will result on the loop filter
16
. Therefore, even if the PFD
12
is working perfectly, the charge pump can affect a static phase error at the output OUT of the PLL
10
.
Referring to
FIG. 2
, a charge pump
30
is shown. The charge pump
30
comprises an inverter
32
, an inverter
34
, a transistor MP
1
, a transistor MP
2
, a transistor MN
2
and a transistor MN
1
. A gate of the transistor MP
1
receives a PMOS source bias signal. A gate of the transistor MP
2
receives a PMOS cascode bias signal. A gate of the transistor MN
1
receives a NMOS cascode bias signal. A gate of the transistor MN
2
receives a NMOS source bias signal.
The circuit
30
is a relatively simple circuit that implements the PLL charge pump with a cascoded PMOS current source and a cascoded NMOS current sink. The current source and sink are cascoded to increase the output impedance in order to maintain the currents IUP and IDN as constant as possible over the output voltage range. The bias voltages for the current source and sink are generated by a set of matched current mirrors, typically from a stable current reference. The signal UPM, the complement of UP, and the signal DN drive inverters that act as low impedance switches to the supply VDD and ground VSS, allowing the source and sink currents to be turned “on” and “off.” For example, when the signal UPM is at low voltage (i.e., UPM=L), the signal UP is driven to nearly the supply VDD, turning on the transistor MP
1
and allowing the current source to conduct current. When the signal UPM is at high voltage (i.e., UPM=H), the signal UP is driven to ground VSS, switching off the transistor MP
1
and halting the flow of current.
The primary disadvantage of the conventional approaches is that some of the non-ideal properties of the circuit can lead to an imbalance in the charge delivered by the current source and sink over a given interval (
T
∫IUP(t)dt≠
T
∫IDN(t)dt), leading to an effective static phase error in the PLL. Two mechanisms of the current imbalance arise from modulation of the gate to source voltage (VSG or VGS) of transistors MP
1
and MN
1
while switching the charge pump. These mechanisms are:
Switching voltage on UP (or DNM) couples across the CGS of MP
1
(or MN
1
) onto the transistor PMOS (or NMOS) source bias, causing a voltage modulation of CGS/(CGS+CBIAS) times the switching voltage on UP (or DNM), VSWITCH-STEP. The modulation of VSG causes a short-term mismatch between charge pump source/sink current and the base reference current used to generate the bias voltages. Since the recovery time of the bias voltages is typically considerably longer than the switching frequency of the charge pump, the source/sink current mismatch can be considerable.
The charge pump switching inverters
32
and
34
also place small glitch voltages (i.e., transient spikes), on the order of 50-100 mV, on the signals UP and DNM when switching the source or sink current “on” or “off”. The glitch is typical for CMOS inverters and is caused by the input rise/fall edge that couples to the output before the inverter MOSFETs can pull the output to VDD or VSS. Because the inverter output is at VDD or VSS when the switching occurs, the glitch pushes the output voltage 50-100 mV above or below VDD or VSS, respectively. The glitch has little effect when the current source (or sink) is being turned “on” because there is no current being conducted.
When the source (or sink) is being turned off, the glitch can have a dramatic effect on output current. The current mirror that biases the transistor MP
1
(or MN
1
) generates a gate voltage based on the supply VDD (or ground VSS) reference at the source of a diode connected MOSFET. Ideally, when the current source (or sink) of the charge pump is turned on, the switching inverters place the supply VDD on the source of the transistors MP
1
(or places ground VSS on the source of the transistor MN
1
) to replicate the bias conditions of the current mirror in order to generate an identical current. When the current source (or sink) is turned off, the source voltage is simply pulled to ground VSS (or the supply VDD for the transistor MN
1
). Before this occurs, however, the source voltage of the transistor MP
1
(or MN
1
) receives the glitch from the switching inverter
32
or
34
, causing a temporary mismatch between the source (or sink) and the bias generator. This causes a current glitch on the source (or sink) that can greatly mismatch the total charge output OUT from the charge pump
30
.
Conventional PL

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