Reduced standby power memory array and method

Details Reduced standby power memory array and method Reduced standby power memory array and method

2001-11-25

2004-01-13

Elms, Richard (Department: 2824)

Static information storage and retrieval

Powering

Data preservation

C365S154000, C327S538000

Reexamination Certificate

active

06678202

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
This invention relates generally to semiconductor devices and more particularly to a reduced standby power memory array and method.
BACKGROUND OF THE INVENTION
Modern electronic equipment such as televisions, telephones, radios and computers are generally constructed of solid state devices. Solid state devices are preferred in electronic equipment because they are extremely small and relatively inexpensive. Additionally, solid state devices are very reliable because they have no moving parts, but are based on the movement of charge carriers.
Solid state devices may be transistors, capacitors, resistors and other semiconductor devices. Typically, such devices are fabricated on a substrate and interconnected to form memory arrays, logic structures, timers and other components of an integrated circuit.
For memory arrays, the speed associated with read and write operations has become increasingly important. Thus, in order to improve the speed for high performance memory arrays, one technique has been to use low threshold voltage transistors. However, disadvantages associated with using low threshold voltage transistors include an increased leakage current for the circuit while in standby mode.
Previous attempts to solve this leakage problem for a typical six-transistor memory cell have included applying a substrate bias to the N-well of p-channel devices. However, this previous solution is less than optimum as the n-channel devices cannot be subjected to a back gate bias without using a separate deep N-well implant to isolate the substrate contact of the n-channel devices. In addition, a deep N-well results in a layout penalty at the edge of the memory array and gate oxide leakage current remains a problem with this solution.
Another attempt to solve the leakage problem involves the use of high threshold voltage transistors. However, this solution requires the use of an additional mask and fails to eliminate the gate leakage current problem, as well as a degradation in performance due to the cell read current.
SUMMARY OF THE INVENTION
In accordance with the present invention, a reduced standby power memory array and method are provided that substantially eliminate or reduce disadvantages and problems associated with previously developed systems and methods. In particular, the present invention provides a memory array with a reduced memory cell voltage and a back gate bias on the load and drive transistors of the memory cells, resulting in a reduced leakage current during standby mode.
In one embodiment of the present invention, a method is provided for reducing standby power in a memory array including a plurality of transistors. Each of the transistors includes a drain, a source and a gate. The method includes providing a memory array column including a plurality of memory cells. Each memory cell includes drive transistors. A current limiting transistor is coupled to the drive transistors. A mode signal is coupled to the current limiting transistor. The mode signal is operable to deactivate the current limiting transistor. The current limiting transistor is deactivated when the mode signal indicates that the memory array column is in a standby mode.
In another embodiment of the present invention, a reduced standby power memory array is provided that includes a plurality of transistors. Each transistor includes a drain, a source and a gate. The memory array includes a memory cell and a current limiting transistor. The memory cell includes drive transistors. The current limiting transistor is coupled to the drive transistors. The current limiting transistor is operable to receive a mode signal. The mode signal is operable to deactivate the current limiting transistor when the cell is in a standby mode.
Technical advantages of the present invention include providing a reduced standby power memory array. In a particular embodiment, the load and drive transistors of the memory cells in the memory array have a back gate bias and the memory cell voltage is decreased while the memory cells are in a standby mode. However, when the memory cells are in an active mode, the back gate bias is removed and the memory cell voltage returns to a normal level. As a result, the leakage current for the memory cells is reduced during standby mode, without negatively affecting the memory cell in the active mode.
Other technical advantages will be readily apparent to one skilled in the art from the following figures, description, and claims.


REFERENCES:
patent: 5583425 (1996-12-01), Rapp et al.
patent: 6038183 (2000-03-01), Tsukude
patent: 6414895 (2002-07-01), Kokubo et al.

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