Reduced signal swing in bit lines in a CAM

Details Reduced signal swing in bit lines in a CAM Reduced signal swing in bit lines in a CAM

2002-07-24

2004-11-16

Nelms, David (Department: 2818)

Static information storage and retrieval

Associative memories

Ferroelectric cell

C365S189050

Reexamination Certificate

active

06819578

ABSTRACT:

BACKGROUND OF THE INVENTION
A content addressable memory (CAM) is a memory device that permits rapid parallel searching of stored data to find a particular data value. In contrast to most other memory formats (such as ROM and RAM memory), which are based on address-driven storage architectures, the typical CAM memory device offers both address-driven and content-driven data access.
Address-driven memory device architectures are well-known. According to an address-driven architecture, during a memory access, a user supplies an address and stores or retrieves data stored at that specific address. For example, in an address-driven data handling scheme, data values may be stored at a particular logical address by specifying the address on an address bus, and supplying data on a data bus to be stored at the specified address. This is the storage mechanism typically found in RAM memory. In the same fashion, data may be retrieved on the data bus in response to a memory address supplied on the address bus.
As noted, the typical CAM memory device can be accessed in both address-driven and content-driven fashion. Storage of data in a CAM may be performed in an address-driven mode, as described above. Additionally, some CAM memory devices allow storage of data in a “first available storage location.” For example a logical flag may be provided for each memory cell of the CAM device, indicating whether a cell contains stored data, or is available to receive new data. When a new data item is presented to the CAM device, each logical flag of the logical flag set is tested simultaneously and an unused storage location is identified. The new data item is then stored in the unused storage location, and the logical flag associated with that location is reconfigured to indicate that the location is in use.
As with data storage, data retrieval in a CAM memory may be performed on an address-driven basis. More importantly, however, CAM memory provides content-driven data retrieval. In a content-driven data search system, a data pattern is presented to the CAM memory device. If the CAM memory device contains a previously stored data item of the same data pattern, that presence is indicated and the location in the CAM where the searched data is stored is returned. The CAM memory device is structured to perform the search on a highly parallel basis, conducting the search on all the data in the CAM simultaneously. Consequently, a CAM can provide search results much more rapidly than an address-driven memory device, in which searches are typically performed serially, one address at a time.
The content-driven data retrieval facility described above makes CAM memory useful in the design of database management, pattern recognition, list management, and telecommunications hardware. CAM is particularly valuable in image and voice recognition systems and in network switching equipment such as, for example, network routers in which CAM memory is used to convert between various address formats. Any technology that requires rapid content searching for an arbitrary data pattern may benefit from the application of CAM technology.
The content-driven data retrieval facility of a CAM memory is typically implemented by providing an array of storage cells connected in an extensive wired-or configuration. This architecture allows a multi-bit data word applied to an input of the CAM device to be compared, virtually simultaneously, with the data words stored in every location of the CAM.
FIG. 1
shows a simplified schematic representation of a CAM memory device, as known in the art. The CAM device
10
includes an array
100
of CAM memory cells
102
coupled in a first direction by complemented
114
and un-complemented
115
bit lines and in a second direction by match lines
110
. The complemented bit lines
114
and un-complemented bit lines
115
are respectively coupled to un-complemented
34
and complemented
34
outputs of respective bit storage locations
30
of an input buffer. Thus, for example, when a “0” is stored in a bit storage location
30
, the un-complemented bit lines
115
exhibits a “0” state and the complemented bit line
114
exhibits a “1”.
The array is arranged in words
103
of memory cells
102
. Each word
103
is a given number of memory cells wide, the width corresponding to a width of the array
105
. The array has a depth
107
equal to the number of words
103
of memory cells in the array. Each of the memory cells
102
includes a memory element
104
with an un-complemented output
111
and a complemented output
113
.
Memory element
104
may be implemented in any of a wide variety of technologies as known in the art. For example, the memory element may be a static memory element as found in conventional static random access memory (SRAM) or a dynamic memory element as found in conventional dynamic random access memory (DRAM).
The un-complemented output
111
of memory element
104
outputs a signal representing a binary value stored within the memory element. The complemented output
113
outputs a signal representing the inverse of the value stored within the memory element
104
.
The memory cell
102
also includes an un-complemented memory element transistor
108
, a complemented memory element transistor
106
, an un-complemented bit line transistor
123
and a complemented bit line transistor
121
. For each memory element, the respective drains of the respective complemented
106
and un-complemented
108
memory element transistors are coupled to a respective match line
110
of the array
100
. A source of the complemented memory element transistor
106
is coupled to a drain of the un-complemented bit line transistor
123
. A source of the un-complemented memory element transistor
108
is coupled to the drain of the complemented bit line transistor
121
. The sources of the complemented
121
and un-complemented
123
bit line transistors are mutually coupled to a source of ground potential
112
. A gate of the complemented memory element transistor
106
is operatively coupled to the respective complemented output
113
of the memory element
104
, so that the state of the memory element transistors reflect the logical state of the memory element. A gate of the un-complemented memory element transistor
108
is operatively coupled to the respective un-complemented output
111
of the memory element
104
. The gates of the complemented bit line transistor
121
and the un-complemented bit line transistor
123
are coupled respectively to the complemented
114
and un-complemented
115
bit lines associated with the respective memory cell
102
.
A plurality of precharge transistors
116
serve to switchingly couple each respective match line
110
to a source
118
of precharge potential. The respective gates of precharge transistors
116
are mutually coupled to a source of a precharge signal
132
. Each match line
110
is coupled to a respective input of one of a plurality of buffer circuits
120
. The buffer circuits
120
serve to amplify an electrical signal on the match line
110
and present an amplified signal at a respective output
122
.
Each bit line
114
,
115
is driven by a respective inverting driver
124
having an input
126
for receiving a data value and an output
128
coupled to the inverting bit line
114
.
The intrinsic capacitance of each match line
110
is represented by capacitor
134
coupled between the bit line
110
and the source of ground potential
112
. Together, the respective plurality of inputs D, of the register bit storage locations
30
, form a data port
130
for receiving an input data value into the CAM device
10
. The data port
130
has a width equal to the width
105
of each data word
103
.
In operation, a search cycle of the CAM begins by precharging the match lines. A logical low signal from the precharge signal source causes the plurality of precharge transistors to conduct current from a source of precharge potential
118
onto respective match lines
110
, charging the respective capacitance
134
of each match line. T

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