Reduced short current circuit

Details Reduced short current circuit Reduced short current circuit

2001-04-17

2002-09-03

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Current driver

C327S112000, C326S083000

Reexamination Certificate

active

06445224

ABSTRACT:

BACKGROUND
A. Technical Field
The present invention relates generally to electronic circuits, and more particularly to short current in standard cell circuits.
B. Background of the Invention
Current circuit design commonly uses standard cell circuits.
FIG. 1
is a block diagram of a generalized standard cell circuit
100
. Typically, the standard cell circuit
100
includes a pre-driver
104
and a driver
108
. An input
102
is coupled to the pre-driver
104
. The pre-driver
104
has an output
106
that is coupled to a driver
108
. The driver
108
has an output
110
.
FIG. 2
shows circuit
200
, a specific embodiment of the standard cell circuit
100
. In the circuit
200
of
FIG. 2
, the pre-driver
104
includes a first transistor
202
and a second transistor
204
. The input
102
is coupled to the gates of both the first transistor
202
and the second transistor
204
. The first transistor
202
is a PMOS transistor and the second transistor
204
is a NMOS transistor. The source of the first transistor
202
is connected to source voltage V
DD
, and the source of the second transistor
204
is connected to ground GND. The drain of the first transistor
202
is connected to the drain of the second transistor
204
, and both drains are coupled to the pre-driver output
106
.
The driver
108
includes a third transistor
206
and a fourth transistor
208
. The gates of the third transistor
206
and the fourth transistor
208
are connected to the pre-driver output
106
. The third transistor
206
is a PMOS transistor and the fourth transistor
208
is a NMOS transistor. The source of the third transistor
206
is connected to source voltage V
DD
, and the source of the fourth transistor
208
is connected to ground GND. The drain of the third transistor
206
is connected to the drain of the fourth transistor
208
. Both the drain of the third transistor
206
and the drain of the fourth transistor
208
are connected to the output
110
.
In operation, the circuit
200
shown in
FIG. 2
has a short current I
S
. This short current I
S
is undesirable because it increases power consumption and produces ground noise.
FIG. 3
shows the circumstances where short current I
S
occurs in the circuit
200
of FIG.
2
. FIG.
3
(
a
) is a graph of the input
102
voltage (“V
IN
”) as a function of time. V
IN
starts low (“V
LOW
”). When V
IN
is at V
LOW
, the first transistor
202
is on and the second transistor
204
is off. At a first time
302
, V
IN
begins to transition to high (“V
HIGH
”). At a second time
304
, V
IN
is high enough so that the second transistor
204
begins to turn on. At the second time
304
, the first transistor
202
has not turned off. Therefore, since both transistors are at least partially on, current flows directly from the source voltage V
DD
to the ground GND, resulting in the short current I
S
.
FIG.
3
(
b
) is a graph of short current as a function of time. As shown in FIG.
3
(
b
), the short current begins to rise at time
304
. As V
IN
continues to transition to V
HGH
, short current I
S
continues to flow, peaking at time
306
. Finally, at time
308
, V
IN
is high enough (as shown in FIG.
3
(
a
)) for the first transistor
202
to turn off. At this point the short current I
S
no longer can flow. At time
310
, V
IN
finishes transitioning to V
HIGH
.
A similar process happens when V
IN
transitions from V
HIGH
to V
LOW
. As shown in FIG.
3
(
a
), between times
310
and
312
, V
IN
is at V
HIGH
. When V
IN
is at V
HIGH
, the first transistor
202
is off and the second transistor
204
is on. At time
312
, V
IN
begins to transition to V
LOW
. At time
314
, V
IN
is low enough for the first transistor
202
to begin to turn on, and the input is not low enough for the second transistor
204
to have turned off. Therefore, both transistors are again at least partially on, so current flows directly from the source voltage V
DD
to the ground GND, resulting in the short current I
S
.
As shown in FIG.
3
(
b
), the short current begins to rise at time
314
, as the first transistor
202
has begun to turn on and before the second transistor
204
has turned off. As V
IN
continues to transition low, short current I
S
continues to flow, peaking at time
316
. Finally, at time
318
, V
IN
is low enough (as shown in FIG.
3
(
a
)) for the second transistor
204
to turn off. At this point the short current I
S
no longer can flow. At time
50
, V
IN
finishes transitioning to V
LOW
.
FIGS.
4
(
a
) through
4
(
d
) show other standard cell circuits that suffer the disadvantages of short current I
S
during operation.
In FIG.
4
(
a
), the circuit
400
is an AND circuit. The AND circuit
400
has a first input
402
and a second input
404
. The first input
402
is coupled to the gates of a pair of transistors
412
and
414
. Transistor
412
is a NMOS transistor and transistor
414
is a PMOS transistor. The second input
404
is coupled to the gates of a pair of transistors
416
and
418
. Transistor
416
is a NMOS transistor and transistor
418
is a PMOS transistor. Transistors
414
and
418
are connected to source voltage V
DD
and to a pre-driver output
406
. Transistor
416
is connected to ground GND and transistor
412
, which is in turn connected to the pre-driver output
406
. The pre-driver output
406
is connected to the gates of transistors
408
and
410
. Transistor
408
is also connected to source voltage V
DD
and to the output
420
. Transistor
410
is also connected to ground GND and to the output
420
.
The AND circuit
400
of FIG.
4
(
a
) is affected by short current I
S
, just as the do circuit
200
of FIG.
2
. For example, the pre-driver output
406
transitions between V
HIGH
and V
LOW
during use of the AND circuit
400
. When such a transition occurs, transistors
408
and
410
are simultaneously on for a period of time, allowing short current I
S
to flow, as explained above in the discussion of FIGS.
3
(
a
) and
3
(
b
).
In FIG.
4
(
b
), the circuit
430
is an OR circuit. The OR circuit
430
has a first input
432
and a second input
434
. The first input
432
is coupled to the gates of a pair of transistors
442
and
444
. Transistor
442
is a NMOS transistor and transistor
444
is a PMOS transistor. The second input
434
is coupled to the gates of a pair of transistors
446
and
448
. Transistor
446
is a NMOS transistor and transistor
448
is a PMOS transistor. Transistor
444
is connected to source voltage V
DD
and to transistor
448
, which is in turn connected to a pre-driver output
436
. Transistors
442
and
446
are connected to ground GND and to pre-driver output
436
. The pre-driver output
436
is connected to the gates of transistors
438
and
440
. Transistor
438
is also connected to source voltage V
DD
and to the output
450
. Transistor
440
is also connected to ground GND and to the output
450
.
The OR circuit
430
of FIG.
4
(
b
) is affected by short current I
S
, just as the circuit
200
of FIG.
2
. For example, the pre-driver output
436
transitions between V
HIGH
and V
LOW
during use of the OR circuit
430
. When such a transition occurs, transistors
438
and
440
are simultaneously on for a period of time, allowing short current I
S
to flow, as explained above in the discussion of FIGS.
3
(
a
) and
3
(
b
).
FIGS.
4
(
c
) and
4
(
d
) are a schematic diagram of a D latch
460
. The D latch
460
has two inputs, a data input
462
and a clock input
480
, and two outputs, Q
1
and Q
2
. The clock input
480
is shown in FIG.
4
(
d
). The portion of the D latch
460
shown in FIG.
4
(
d
) receives the clock input
480
and produces outputs C
1
and C
2
, which are connected to the rest of the D latch
460
at the locations shown in FIG.
4
(
c
).
The D latch
460
of FIGS.
4
(
c
) and
4
(
d
) is affected by short current I
S
, just as the circuit
200
of FIG.
2
. For example, there are numerous transistor pairs
464
,
466
,
468
,
470
,
472
,
474
, and
476
in the D latch. In each of these transistor pairs
4

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