Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Having air-gap dielectric
Reexamination Certificate
1998-12-08
2001-10-30
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Having air-gap dielectric
C438S422000, C438S668000, C438S619000
Reexamination Certificate
active
06309946
ABSTRACT:
SUMMARY OF THE INVENTION
According to the invention, a void is defined between adjacent wiring lines to minimize RC coupling. The void has a low dielectric value approaching 1.0. The void is space absent solid and liquid material. In various embodiments, the space is a vacuum or is filled with a gaseous substance having desired dielectric properties.
According to one method of the invention, a hollow silicon dioxide sphere defines the void. The sphere is fabricated to a known inner diameter, wall thickness and outer diameter. Preferably, the wiring line height is a multiple of the line spacing, or the spacing is a multiple of the wiring line height. Spheres of a unit dimension then fill the spacing to achieve one or more rows (or columns) of spheres.
According to one aspect of the method, the spheres are rigid enough to withstand the mechanical processes occurring during semiconductor fabrication.
The spheres are held in place during the semiconductor fabrication processes by a binder. According to another aspect of the method, the spheres and binder withstand elevated temperatures up to a prescribed temperature range. At or above a desired temperature, the binder is baked away leaving the sphere intact and in place.
According to another method of the invention, the adjacent wiring lines are “T-topped” (i.e., viewed cross-sectionally). In a specific embodiment the cross section appears as a “T” or as an “I.” Dielectric fill is deposited in the spacing between lines by a chemical vapor deposition (“CVD”) or other deposition process. As the dielectric material accumulate on the wiring line and substrate walls, the T-tops grow toward each other. Eventually, the T-tops meet sealing off an internal void. Using controlled processes, the void is reliably defined to a known size and shape.
According to preferred embodiments, a spacing between adjacent wiring lines of a semiconductor substrate includes a first material which defines a void. The void has no solid material or liquid material, but may include a gas. Also, the void is characterized by a dielectric constant which is lesser than the dielectric constant of the first material. In one embodiment, a plurality of discrete hollow objects fill the spacing. Each one of the plurality of objects is a hollow, rigid, silica sphere which defines a void. Each sphere is of substantially the same dimensions. The spacing between adjacent lines is approximately a first multiple of sphere outer diameter. The height of the adjacent wiring lines is approximately a second multiple of sphere outer diameter. Preferably, either one, but not both, of the first multiple and the second multiple are greater than one.
According to a preferred embodiment of one method, a void is controllably-defined in spacing between adjacent wiring lines of a semiconductor substrate. At one step, a plurality of discrete hollow silica spheres are applied to the spacing. At another step, excess spheres are removed from areas other than the spacing. At another step, material is deposited over the wiring lines and spheres. For one method, the spheres are applied as part of a film, including a binder. The binder holds the objects in place within the spacing. For one method, the excess spheres are removed by performing a chemical mechanical polishing (“CMP”) process. Preferably, the deposition step occurs at a temperature sufficient to break down the binder while leaving the spheres in place and intact.
According to another preferred embodiment, a void is controllably-defining in spacing between adjacent wiring lines of a semiconductor substrate using an alternative method. At one step, a T-top configuration is etched at each of the adjacent wiring lines. At another step, dielectric material is deposited onto the substrate and adjacent wiring lines. The deposited material accumulates about the T-top to seal off a void in the spacing. The void forms with dimensions determined by the spacing, wiring line height, and undercut of the T-tops. For various alternatives, the wiring line cross-sections after T-topping resemble and “I” or a “T” configuration.
According to one advantage of the invention, the controllably-defined void(s) reduce the dielectric value in the spacing between adjacent wiring lines. As a result, the RC delay is comparatively reduced. According to another advantage, the reduced dielectric is achieved for conventional (e.g., ≧1.0 microns) or reduced line spacing (e.g., <1.0 microns; <0.5 microns). With sphere outer diameters achieved at 0.1 microns, the method has the advantage of being beneficial for line spacing as low as 0.1 micros. As technologies enable smaller spheres, the method also becomes applicable for smaller line spacings. These and other aspects and advantages of the invention will be better understood by reference to the following detailed description taken in conjunction with the accompanying drawings.
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Wolf et al., Silicon Processing for the VLSI Era vol. 1: Process Technology, 1986, Lattice Press, pp. 520-523, 161-164, 168, and 171.
Micro)n Technology, Inc.
Rocchegiani Renzo N.
Smith Matthew
TraskBritt
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