Reduced power usage in a memory for a programmable logic device

Details Reduced power usage in a memory for a programmable logic device Reduced power usage in a memory for a programmable logic device

2008-04-01

2008-04-01

Auduong, Gene N. (Department: 2827)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S189011, C365S230060

Reexamination Certificate

active

11317324

ABSTRACT:
A method and system to reduce power usage of memory within a programmable logic device (PLD) is disclosed. In one embodiment, a memory block is formed from a plurality of memory sub-blocks. A data management circuit is used to programmably couple bitlines and/or wordlines to a selected number of memory sub-blocks necessary for respective read/write operations. During a respective read operation, the data management circuit uses row and/or column addresses to determine which memory bitlines and/or wordlines, and memory sub-blocks are essential in the read operation, leaving other non-essential bitlines and/or wordlines, and memory sub-blocks idle, thereby conserving power usage of the entire memory block. In one embodiment, a during respective read operation, a series of programmable pass-gates are used to selectively de-couple bitlines and/or wordlines, and memory sub-blocks that are not essential to the read operation.

REFERENCES:
patent: 5390333 (1995-02-01), Pritt et al.
patent: 6127843 (2000-10-01), Agrawal et al.
patent: 6462998 (2002-10-01), Proebsting
Azizi, Navid et al.; “Low-Leakage Asymmetric-Cell SRAM”; University of Toronto, 4 pages, unknown date.
“Memory technology information page”;2005, ePanorama.net, http://www.epanorama.net/links/memory.html, 12 pages.

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