Static information storage and retrieval – Powering – Conservation of power
Reexamination Certificate
2007-04-26
2010-02-16
Mai, Son L (Department: 2827)
Static information storage and retrieval
Powering
Conservation of power
C365S226000, C365S230030
Reexamination Certificate
active
07663961
ABSTRACT:
A reduced-power memory (such as for a cache memory system of a processor or a microprocessor) provides per-sector power/ground control and early address to advantageously reduce power consumption. Selective power control of sectors comprised in the reduced-power memory is responsive to a subset of address bits used to access the memory. The selective power control individually powers-up a selected one of the sectors in response to an access, and then powers-down the selected sector when the access is complete. The power-up is via an increase of differential between power and ground levels from a retention differential to an access differential. Time needed to vary the differential is masked by providing address information used by the selective power control in advance of providing other address information. For example, in a cache, a tag access is overlapped with power-up of a selected sector, thus masking latency of powering up the selected sector.
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Favor John Gregory
Fung Daniel
Moll Laurent R.
Rowlands Joseph B.
Mai Son L
Osha • Liang LLP
Sun Microsystems Inc.
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