Reduced power consumption clock network

Details Reduced power consumption clock network Reduced power consumption clock network

2005-12-13

2005-12-13

Nguyen, Minh (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S293000, C713S320000

Reexamination Certificate

active

06975154

ABSTRACT:
An exemplary reduced-power-consumption network includes a frequency divider coupled through global clock lines to a plurality of double-edge triggered registers. Another exemplary network includes a plurality of individually programmable frequency dividers coupled through local clock lines to a plurality of double-edge triggered registers.

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patent: 6720810 (2004-04-01), New
R. Hossain et al., “Low Power Design Using Double Edge Triggered Flip-Flops” IEEE Transactions VLSI Systems, vol. 2. No. 2, pp. 261-265, Jun. 1994.
S.H. Unger, “Double-Edge-Triggered Flip-Flops”, IEEE Transactions on Computer, vol. c-30, No. 6, pp. 447-451, Jun. 1981.

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