Reduced power consumption bi-directional buffer

Details Reduced power consumption bi-directional buffer Reduced power consumption bi-directional buffer

2000-12-08

2003-07-08

Nguyen, Minh (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Current driver

C327S404000, C327S562000, C326S083000, C330S257000, C330S288000

Reexamination Certificate

active

06590433

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to electronic circuits and specifically to bi-directional buffers.
BACKGROUND
A typical bi-directional buffer facilitates data transfer between devices. For example, a bi-directional buffer may be coupled between a network bus and a computer.
FIG. 1
is a simplified block diagram of a typical bi-directional buffer, generally designated
1
, coupled between an external device and a computer. External device
3
may be any external device such as a network coupled to bi-directional buffer
1
by a cable or a backplane. Computer
5
may be any computer, such as a personal computer, a server, or several computers or servers, coupled to bi-directional buffer
1
by a cable or backplane. Bi-directional buffer
1
, receives data from an external device
3
during a receive mode. This data is transferred to computer
5
. Bi-directional buffer
1
transmits data to external device
3
from computer
5
during a transmit mode. Enabling signals
6
determine whether bi-directional buffer
1
is in the transmit mode or the receive mode. Input stage
2
typically receives data from an external device
3
during the receive mode and output stage
4
typically provides data to the external device during the transmit mode.
Many older bi-directional buffers, in an effort to conserve power, discontinued DC current flow to a stage if it is not active (i.e., input stage not receiving or output stage not transmitting). However, turning DC current on and off takes time. As data rates became faster, the time required to turn a stage on and off could not be tolerated. Thus, in an attempt to meet the demand for higher data rates, DC current is not discontinued (i.e., input and output stages are not turned off and on). In order to concurrently conserve power and increase data rates, DC current is maintained during the receive and transmit modes, the variation in signal voltages is kept relatively small, and terminal impedances are matched to the coupled external device. However, because DC current is supplied to the buffer during an inactive period, power is wasted. Thus, it is desired to have a buffer that can turn current on and off quickly enough to meet current data rates.
SUMMARY OF THE INVENTION
An electronic circuit includes a current mirror and two stages. The current mirror provides a current, which is responsive to at least one low power signal. The first stage receives the current from the current mirror and directs the current to either a first voltage potential or to the second stage. The current is directed in response to at least one enable signal. If the current is directed to the second stage, the second stage receives the current and directs it to one of a plurality of output nodes. Directing of the current in the second stage is responsive to at least one control signal.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.


REFERENCES:
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patent: 6034551 (2000-03-01), Bridgewater, Jr.
patent: 6064229 (2000-05-01), Morris

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