Reduced power bit line selection in memory circuits

Details Reduced power bit line selection in memory circuits Reduced power bit line selection in memory circuits

1999-12-29

2002-05-21

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Interconnection arrangements

C365S205000, C365S202000, C365S207000, C365S230030

Reexamination Certificate

active

06392911

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates in general to memory integrated circuits. In particular, this invention relates to a method and apparatus for reducing power consumption during bit line selection in memory circuits.
Memory circuits such as dynamic random access memories (DRAMs) are generally made up of a large number of memory cells arranged in the form of a matrix or array with rows and columns.
FIG. 1
is a simplified block diagram of a conventional DRAM. In this typical example, memory access to the DRAM usually takes place as follows. The address buffer first reads the row address and then the column address. The addresses are passed to their respective decoders for decoding. Once decoded, the memory cell addressed outputs the stored data, which is amplified by a sense amplifier and transferred to a data output buffer by an I/O gate.
The central part of the DRAM is the memory cell array
100
, which is where the data are stored.
FIG. 2
is a simplified block diagram of a conventional DRAM showing an illustrative structure of the memory cell array
100
. The memory cell array
100
is made up of many unit memory cells, each of which is usually individually addressable and used to store a bit. Unit memory cells are defined by word lines WLx (or rows) and bit lines BLx (or columns). The unit memory cell has a capacitor which holds the data in the form of electrical charges, and an access transistor which serves as a switch for selecting the capacitor. The transistor's gate is connected to the word line WLx. The source of the access transistors are alternately connected to the bit lines BLx. At this level, memory access begins when a word line is selected (via the decoding of a row address) thereby switching on all the access transistors connected to that word line. In other words, all the unit memory cells in that particular row are turned on. As a result, charges in the capacitor within each unit memory cell are transferred onto the bit lines causing a potential difference between the bit lines. This potential difference is detected and amplified by a sense amplifier. This amplified potential difference is then transferred to the I/O gate activated based on the column address, which in turn transfers the amplified signal to the data output buffer.
The precharge circuit plays a significant role in detecting memory data during the course of a memory access operation. In advance of a memory access and the activation of a word line, the precharge circuit charges all bit line pairs up to a certain potential which usually equals to half of the supply potential, that is, Vdd/2. The bit line pairs are short-circuited by a transistor so that they are each at an equal potential. The precharging and potential equalization by the precharging circuit is important due to the disparate difference in capacitance between the bit lines and the storage capacitor. Since the capacitance of the storage capacitor is far less than that of the bit lines, when the storage capacitor is connected to the bit lines via the access transistor, the potential of the bit line changes only slightly, typically by 100 mV. If the storage capacitor was empty, then the potential of the bit line slightly decreases; if charged, then the potential increases. The activated sense amplifier amplifies the potential difference on the two bit lines of the pair. In the first case, it draws the potential of the bit line connected to the storage capacitor down to ground and raises the potential of the other bit line up to Vdd. In the second case, the bit line connected to the storage capacitor is raised to Vdd and the other bit line decreased to ground.
Without the precharging circuit, the sense amplifier would need to amplify the absolute potential of the bit lines. However, because of the relatively small potential change between the bit lines, the amplifying process would be much less stable and unreliable.
It should be noted that as the access transistors remain on by the activated word line, the accessed data are written back into the memory cells of one row. Therefore, the accessing of a single memory cell simultaneously leads to a refreshing of the whole word line. After the data output is completed, the sense amplifiers and the row and column decoders are disabled and the I/O gate block is switched off. At that time, the bit lines are still on the potentials according to the accessed data. The refreshed memory cells along the same row are disconnected from the bit lines by the disabled word line. The precharge circuit is activated to lower and increase respectively the potentials of the bit lines to Vdd/2 and equalize them again. The memory array is then ready for another memory access.
In addition, as previously mentioned, the data are stored in the form of electrical charges in the storage capacitor. Ideally, the charges in the storage capacitor should remain indefinitely. However, as a practical matter, the storage capacitor discharges over the course of time via the access transistor and its dielectric layer thereby losing the stored charges and the represented data. Hence the storage capacitor must be refreshed periodically. As discussed above, during the course of a memory access, a refresh of the memory cells within the addressed row is automatically performed. As is commonly known in the art, three refresh methods are typically used, namely, the RAS-only refresh, the CAS-before-RAS refresh, and the hidden refresh.
Due to physical constraints, the size of a memory array
100
is limited. Thus, in order to increase memory capacity, memory arrays
100
are typically stacked together to provide for the desired capacity.
FIG. 3
is a simplified block diagram showing a typical structure having stacked memory arrays
100
. The sense amplifiers
102
are shared by adjacent pairs of memory arrays
100
but otherwise perform the same function as mentioned above. The precharge circuit (not shown) which performs the precharge and equalization functions as mentioned above may be incorporated into a sense amplifier.
Referring to
FIG. 3
, a number of stacked memory cell arrays
100
(“MCAs”) are used to provide data storage. As is commonly known in the art, the number of MCAs to be used depends on the desired memory capacity and other system constraints. In
FIG. 3
, three representative MCAs
100
a
,
100
b
,
100
c
are shown. Each MCA
100
has pairs of bit lines, for example, bit line pair bl(
0
) and bl({overscore (
0
)}), accessible on its either side.
Positioned between an adjacent pair of MCAs, such as MCAs
100
a
,
100
b
and MCAs
100
b
,
100
c
, are a row of bit-line sense amplifiers
102
(each a “BLSA”). The number of BLSAs
102
corresponds to the number of bit line pairs of each MCA
100
. Each BLSA
102
is electrically connected to both members of the adjacent pair of MCAs such as MCAs
100
a
,
100
b
. More specifically, each BLSA
102
is coupled to a bit line pair, for example, bl(
0
) and bl({overscore (
0
)}) of a MCA
100
via two switches, such as transistors
104
. Hence, each BLSA
102
is connected to four transistors
104
, in total, two transistors for each MCA
100
.
A bit-line select controller
106
(“BLSC”) is used to control the operation of each row
108
of BLSAs
102
. Each BLSC
106
has two control lines
110
a
,
110
b
extending therefrom. One control line
110
a
is connected in parallel to the gate of all the transistors
104
connecting the row
108
u
of BLSAs
102
to one member MCA
100
a
of the adjacent pair, while the other control line
110
b
is similarly connected to all the transistors
104
connecting the row
108
u
of BLSAs
102
to the other member MCA
100
b
of the adjacent pair.
FIGS. 4
a-c
are various voltage level diagrams. Specifically,
FIG. 4
a
shows the voltage level of successively activated word lines within one MCA(i)
100
b
. For each active cycle, the potential of each word line, for example, WL(n), first goes from ground to Vpp and then back down to ground before the next active cycle begins. The voltage Vpp is a boosted v

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