Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – For high frequency device
Reexamination Certificate
1998-08-25
2001-10-30
Potter, Roy (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
For high frequency device
C257S774000
Reexamination Certificate
active
06310394
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a technique for reducing parasitic capacitances in high speed schottky barrier and p-n junction devices while improving manufacturing yield and performance.
BACKGROUND OF THE INVENTION
In many applications of rf and microwave frequency devices, improvement lies solely in the ability to modulate or detect very weak signals. In the microwave and rf frequency range, very sensitive receivers are essential to progress being made in radio frequency communications and radar systems. Junction diodes designed specifically for parametric interaction are varactor diodes. High frequency varactor and schottky diodes are generally gallium arsenide based, while in many applications varactor and schottky diodes are silicon based devices.
As the frequency response of the devices is increased, parasitic elements of capacitance and inductance must be minimized to a large extent in the design of the device. To this end, capacitive as well as parasitic inductance elements can have dramatic ill effects on the frequency response of a device.
Turning first to the capacitance of a given device, there are basically three areas where capacitance can arise. First, is the junction capacitance associated with the junction between distinct layers of the semiconductor device. Generally in order to reduce the junction capacitance of the given device, junction widths are reduced as greatly as possible. However, often the tradeoff between the reduction in junction capacitance and the increase in series resistance by reduction of junction width must be considered with great scrutiny. Furthermore, the capacitance associated with the packaging of the device must be considered and reduced as much as possible. Finally, bond pad capacitance, the focus of the present invention, occurs at the overlay structure of the junction, that is the bond pad with the metallization of the device.
Bond pad parasitic capacitance like other sources of capacitance is directly dependent upon the area of the bond pad. One possible solution for reducing bond pad capacitance has been to reduce the area of the bond pads themselves. In standard processing techniques, as is shown in
FIG. 1
, a standard varactor has a bond pad metalization on the order of one mil in width. This has the intrinsic benefit of reducing the capacitance associated with the bond pad and thereby improving the frequency response of the varactor. The package inductance plays an important role in the rf performance of the tuning varactor. In order to obtain maximum Q-factor (Quality Factor) especially at high frequencies, 3 mil bonding ribbon is preferred over bonding wire. Bonding a 3 mil ribbon to a 1 mil mesa GaAs junction is a difficult task and results in low production yield. Also, the reliability of the resultant device could be compromised. To this end, due to the relatively small area of the bond pad, the resultant manufacturing yields are generally very low. It could also result in a weak bond and a hence an unreliable contact to the device. This unreliability of the electrical contact can occur through the actual initial bonding to the device as well as a failure during the bond pull test which is performed during the reliability testing of the device.
In theory, the use of a one mil wirebond which is exactly aligned to the one mil bond pad produces a connection which is certainly reliable and strong enough to withstand a bond pull test. However, in practice this is generally not achieved. To this end, very often misalignment occurs and bond pull tests result in failure of the connection between the wirebond and the bond pad. Additionally, the use of wirebonds to effect the electrical connection to the bond pad also results in an increased inductance, a parasitic inductance to the device. This parasitic inductance degrades the performance of certain devices, for example, the turning ability of varactor diodes. Bond ribbons, an electrical material having a width on the order of three mils as opposed to the one mil wirebond, are used in applications where the inductance associated with wire bonds must be minimized. Bond ribbons give a lower inductance per unit length than the counterpart wirebond.
There are a couple of considerations that must be taken into account when determining the most effective method to effect electrical connection between the bond pad and the external circuit. First, when considering a bond ribbon, there is yet an even lower reliability and thus a reduced yield even when compared to the wire bond when using the standard 1 mil diameter bond pad. To this end, a 3 mil bond ribbon attached to a 1 mil diameter bond pad results in a high rate of peel-off during bond pull testing. This is a direct result of the overhang of the bond ribbon. This is shown more clearly in
FIG. 1
, a prior art varactor having the bond ribbon attached to the top bond pad. In order to properly effect a good bond ribbon/bond adhesion, it is necessary to increase the diameter of the bond pad making the bond strength between the bond ribbon and the bond pad optimal. Furthermore, in order to fabricate semiconductor diodes in high volume and at low cost, it is necessary to employ automatic bonding machines But these bonding machines are based on pattern recognition principles and thus require a large bonding area on the order of at least 4 mils in diameter for effective operation. Accordingly, the diameter of the bond pad must be made larger than is done conventionally. This, as stated above will result in an increased capacitance associated with the bond pad which has the attendant disadvantages on high speed devices. Finally, it is of interest to note that in certain applications the wire bond is a preferred means to effect electrical connection from the bond pad to the external circuit, and accordingly a larger bond pad diameter would enable more reliable wire bond adhesion and thus would improve the reliability of the bond and thus the yield.
Accordingly, what is needed is a technique for effecting electrical connections at the device level for high speed devices which both reduces the overall bond pad capacitance as well as improves the bond strength. The resulting device has improved manufacturing yield as well as the improved performance required through reduced parasitic capacitance and inductance.
SUMMARY OF THE INVENTION
The present invention relates to a technique for bonding ribbon/wire to a bond pad on a semiconductor device which enables a strong bond between the bond ribbon and the bond pad by virtue of a relatively large bond pad, while reducing as greatly as possible the capacitance associated with the bond pad.
The semiconductor device of the present invention is processed with a standard width bond pad of about one mil. By having a relatively small bond pad width, the intrinsic capacitance of the bond pad, a parasitic capacitance, is kept to a minimal level. Thereafter, a layer of material, preferably benzocyclobutene (BCB) is deposited about the device and associated bond pad. A via is etched in the BCB by standard technique to enable access to the bond pad. Thereafter, a layer of metal is deposited along the side walls of the etched via and on top of the BCB. This layer of conductive material, preferably metal, has a relatively large area to enable a secure bond between the bond ribbon and the bond pad. This layer of metal has a diameter preferably larger than the diameter of the bond ribbon to assure a strong adhesion of the bond ribbon to the bond pad layer. However, by virtue of the BCB layer, there is no significant increase in the parasitic capacitance associated with the bond pad. To this end, the BCB material is chosen because of its relatively low dielectric constant when compared to other materials suitable in this application, for example, silicon dioxide. Furthermore, BCB can be deposited in a relatively thick layer, which also reduces the capacitance which is associated with the bond pad structure. The BCB process of the present invention is described in the present disclosure for
Anand Yoginder
Chinoy Percy Bomi
Potter Roy
Tyco Electronics
LandOfFree
Reduced parasitic capacitance semiconductor devices does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Reduced parasitic capacitance semiconductor devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Reduced parasitic capacitance semiconductor devices will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2617784