Reduced parallel and pipelined high-order MIMO LMMSE...

Details Reduced parallel and pipelined high-order MIMO LMMSE... Reduced parallel and pipelined high-order MIMO LMMSE...

2004-11-24

2009-02-17

Ghayour, Mohammad H (Department: 2611)

Pulse or digital communications

Equalizers

C375S147000, C375S232000

Reexamination Certificate

active

07492815

ABSTRACT:
Disclosed is a LMMSE receiver that restores orthogonality of spreading codes in the downlink channel for a spread spectrum signal received over N receive antennas. The FFT-based chip equalizer tap solver reduces the direct matrix inverse of the prior art to the inverse of some submatrices of size N×N with the dimension of the receive antennas, and most efficiently reduces matrix inverses to no larger than 2×2. Complexity is further reduced over a conventional Fast Fourier Transform approach by Hermitian optimization to the inverse of submatrices and tree pruning. For a receiver with N=4 or N=2 with double oversampling, the resulting 4×4 matrices are partitioned into 2×2 block sub-matrices, inverted, and rebuilt into a 4×4 matrix. Common computations are found and repeated computations are eliminated to improve efficiency. Generic design architecture is derived from the special design blocks to eliminate redundancies in complex operations. Optimally, the architecture is parallel and pipelined.

REFERENCES:
patent: 6954495 (2005-10-01), Piirainen
patent: 2003/0026345 (2003-02-01), Muharemovic et al.
patent: 2004/0228392 (2004-11-01), Zhang et al.
patent: 2005/0053172 (2005-03-01), Heikkila
patent: 2005/0180493 (2005-08-01), Hooli et al.
patent: 2005/0281323 (2005-12-01), Mailaender
Guo et al., Scalable FPGA Architectures for LMMSE-based SIMO Chip Equalizer in HSDPA Downlink, Nov. 9-12, 2003, Signals, Systems and Computers, 2003. Conference Record of the Thirty-Seventh Asilomar Conference on, vol. 2, pp. 2171-2175.
Guo et al., FFT-Accelerated Iterative MIMO Chip Equalizer Architecture for CDMA Downlink, Mar. 18-23, 2005, Acoustics, Speech, and Signal Processing, 2005. Proceedings, (ICASSP '05). IEEE International Conference on, vol. 3, pp. 1005-1008.
Guo et al., Efficient MIMO Equalization for Downlink Multi-Code CDMA: Complexity Optimization and Comparative Study, Nov. 29-Dec. 3, 2004Global Telecommunications Conference, 2004, GLOBECOM '04. IEEE, vol. 4, pp. 2513-2519.
Foschini, Gerard J., “Layered Space-Time Architecture for Wireless Communication in a Fading Environment When Using Multi-Element Antennas”, Bell Labs Technical Journal, 1996, pp. 41-59.
Hooli, Jari, et al., “Chip-Level Channel Equalization in WCDMA Downlink”, BURASIP Journal on Applied Signal Processing, 2002, pp. 757-770.
Guo, Yuanbin, et al., “Efficient MIMO Equalization for Downlink Multi-Code CDMA: Complexity Optimization and Comparative Study”, IEEE 2004, pp. 2513-2519.
Guo, Yuanbin, et al., “Scalable FPGA Architectures for LMMSE-based SIMO Chip Equalizer in HSDPA Downlink”, 37thIEEE Asilomar Conference on Signals, Systems and Computers, 2003, 5 pages.
Kermoal, Jean Philippe et al., “A Stochastic MIMO Radio Channel Model With Experimental Validation”, IEEE Journal On Selected Areas In Communications, vol. 20, No. 6, Aug. 2002, pp. 1211-1226.
Golden, G.D. et al., “Detection algorithm and initial laboratory results using V-BLAST space-time communication architecture”, Electronics Letters, vol. 35, Jan. 1999, pp. 14-15.
Wiesel, Ami et al., “Turbo linear dispersion space time coding for MIMO HSDPA systems”, 12th1st Summit on Mobile and Wireless Communications, Jun. 15-18, 2003, Aveiro, Portugal, 5 pages.
Radosavljevic, Predrag et al., “ASIP Architecture Implementation of Channel Equalization Algorithms for MIMO Systems In WCDMA Downlink”, IEEE 2004, pp. 1735-1739.
Krauss, Thomas P., et al. “MMSE Equalization For Forward Link In 3G CDMA: Symbol-Level Versus Chip-Level”, IEEE 2000, pp. 18-22.
Heikkila, Markku J. et al., “Space-Time Equalization Using Conjugate-Gradient Algorithm In WCDMA Downlink”, IEEE 2002, pp. 673-677.
Zhang, Jianzhong, et al., “Efficient Linear Equalization for High Data Rate Downlink CDMA Signaling”, IEEE2003, pp. 141-145.

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