Reduced overhead for clock testing in a level system scan design

Details Reduced overhead for clock testing in a level system scan design Reduced overhead for clock testing in a level system scan design

1976-06-30

1978-01-31

Malzahn, David H.

Boots, shoes, and leggings

307221R, 364900, G06F 738

Patent

active

040719022

ABSTRACT:
The disclosure relates to LSSD systems for use in digital computers and the like. More particularly, to an organization of logic in such systems to render the clock networks testable with minimal overhead. The advantages of the practice of the invention are particularly apparent and enhanced when the invention is employed in a Level Sensitive Scan Design (LSSD) System generally of the type disclosed in U.S. Pat. No. 3,783,254 and U.S. patent application Ser. No. 701,052, filed June 30, 1976.

REFERENCES:
patent: 3851187 (1974-11-01), Pao et al.
patent: 3983538 (1976-09-01), Jones
J. E. Elliott et al. "Array Logic Processing" IBM Tech. Disclosure Bulletin vol. 16, No. 2 July 1973, pp. 586-587.

Affiliated with

Also associated with

Rating

Reduced overhead for clock testing in a level system scan design does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Reduced overhead for clock testing in a level system scan design, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Reduced overhead for clock testing in a level system scan design will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2080128