Fishing – trapping – and vermin destroying
Patent
1995-05-25
1997-02-18
Niebling, John
Fishing, trapping, and vermin destroying
437193, 437 41, H01L 2128
Patent
active
056041578
ABSTRACT:
A method for fabricating MOSFET devices, with narrow gate structures, and narrow spaces between gate structures, has been developed. The addition of a rough surfaced silicon layer, as part of the gate structure, minimizes the amount of reflective and scattered light, resulting during the gate photolithographic processing. The reduction in reflective and scattered greatly enhances the ability to achieve sub-micron lines and spaces. The rough surfaced silicon can remain as a part of the gate structure, and is obtained by chemical vapor deposition of either an amorphous silicon, or a hemi-spherical grained silicon film.
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Chine Lou G.
Dai Chang-Ming
Ho Jau-Hwang
Bilodeau Thomas G.
Industrial Technology Research Institute
Niebling John
Saile George O.
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