Reduced-mask, split-polysilicon CMOS process, incorporating stac

Details Reduced-mask, split-polysilicon CMOS process, incorporating stac Reduced-mask, split-polysilicon CMOS process, incorporating stac

1991-11-21

1992-07-28

Thomas, Tom

Fishing, trapping, and vermin destroying

437 47, 437 48, 437 57, 437 60, 437228, 437919, 357 236, H01L 2170

Patent

active

051340852

ABSTRACT:
This invention constitutes a 10-12 mask, split-polysilicon process for fabricating dynamic random access memories of the stacked capacitor type for the one-megabit generation and beyond. The process flow is characterized: reduced mask count due to the elimination of the N+ and p+ source-drain masking layers via the split polysilicon technique; an option to further reduce wafer processing by allowing the LOCOS stress relief (pad) oxide layer to later function as the transistor gate dielectric layer; N-channel device optimization via self-aligned punch-through and lightly-doped-drain (LDD) implants, without the addition of extra P-channel masking steps via the split poly approach; use of semi, self-aligned contact of bottom cell plate to access gate diffusion allowing tight spacing between bottom cell plate buried contact and access gate polysilicon; improved refresh characteristics achieved by avoiding reduction of isolation thickness due to the spacer oxide etch; improved refresh characteristics achieved by protecting the sensitive areas of the storage node from damage typically caused by a spacer oxide etch; improved refresh characteristics achieved by eliminating the high-dose N-channel source/drain implantation from the storage node side of the access transistor gate; and improved immunity to soft error upset achieved through the use of an optional self-aligned "Hi-C" implant that is performed without the addition of an extra masking step.

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patent: 4987089 (1991-01-01), Roberts et al.
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patent: 5032530 (1991-07-01), Lowrey et al.
patent: 5071783 (1991-10-01), Taguchi et al.

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