Reduced latency wide-I/O burst architecture

Details Reduced latency wide-I/O burst architecture Reduced latency wide-I/O burst architecture

2002-09-13

2004-06-22

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Addressing

Cartesian memories

C365S236000

Reexamination Certificate

active

06754135

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates in general to high speed computer systems where memory chips are used as L2 or L3 cache memory for the microprocessor. More particularly, the invention relates to memory chips where data is transferred from the memory to the processor and from the processor to the memory in data bursts of four or more words where the burst of data can be of any particular addressing order. This invention improves the latency of the burst of data by the memory system and simplifies the on-chip circuit implementation.
2. Background of the Invention
Most workstation and server computer systems require a memory hierarchy to process and store data in the most efficient manner. Typically, the furthest away the memory resides from the processor, the slower it is, but also the densest it becomes. Likewise, the closest memory is to the processor, the greater the performance. Most memory hierarchies have three or four memory levels, also known as L1, L2, L3 and L4. The L1 and L2 memory is typically embedded in the processor, thus their capacity is normally limited to 16 Mb or less. The L1 and L2 memory is typically in the form of Static Random Access Memory (SRAM), since its performance requirements have to keep up with processor cycle times. Once the memory level moves off-chip, its performance can no longer keep up with the processor cycle times because of I/O bandwidth limitations. Typically, L3 memories are operated at a fraction of the processor cycle time. Nonetheless, L3 performance as measured by core cycle time and latency may still be the bottleneck for the entire cache subsystem. As a result, L3 cache have typically used SRAM because of its superior performance over commodity Dynamic Random Access Memory (DRAM), despite the density disadvantages of SRAM. When gauging memory performance, three factors come into play: I/O bandwidth (also known as data rate), random cycle time and latency. Data rate refers as the time that it takes to transfer data words from the memory to the processor (and vice-versa). Random cycle refers to the period between random addresses as captured by the memory, and finally, latency refers to the time that it takes for the memory to start producing data from the time that a random address is captured.
Emerging process technologies are enabling DRAM cells to be embedded into logic-based processes. Logic-based DRAM performance can be as much as 4× faster than DRAMs fabricated using commodity-DRAM processes. Furthermore, new DRAM architectures such as Reduced-Latency DRAM (RLDRAM) or Fast-Cycle DRAM (FCRAM) are offering significant improvements in performance over commodity DRAM. The emergence of faster DRAM is opening the door for applications typically suitable for SRAM only. An example of such memory device is a DRAM built in a logic-based product that offers a 4× the density improvement over SRAM (built in the same lithography). Although the core cycle time of the fast DRAM is still about 4× slower than that of the fastest SRAMs, the data rate and latency of the fast DRAM is fast approaching that of the SRAM's. Such fast DRAM are being used for L3 cache applications with data rates approaching that of fast SRAMs.
The task of making fast DRAM data rates is accomplished by an increase in burst length. For example, a fast SRAM may have a random cycle time of 2 ns and a data burst of two. Data can be output every 1 ns on both rising and falling edges of the clock (Double-Data-Rate (DDR) to provide a 1 ns data rate. Every 2 ns a random address is presented to the SRAM and data is output in a burst of two within the 2 ns period. A fast DRAM with a 4× slower core cycle-time can achieve the same data rate with an increased burst length of eight. The fast DRAM core cycle time is 4× that of the SRAM in the example above, or 8 ns. Every 8 ns a random address is presented to the fast DRAM. Every 8 ns, data is output in a burst of eight, producing 1 ns data rates.
Such increases in burst length to achieve the same data rates as that of SRAM do not come without architectural complexities. For example, a typical fast SRAM has an I/O configuration of 36 bits (×36). In a burst of two, two sets of 36 bits have to be pre-fetched from the memory array for every core cycle. The two 36 bit words are formatted and prioritized according to the initial burst base address. In order for the DRAM to maintain the same data rate as the SRAM, eight 36 bit words have to be pre-fetched on every DRAM core cycle. The complexity and performance impact arising from prioritizing the eight 36 bit words so that the correct burst order is maintained is much greater than that of the SRAM. The eight 36-bit burst order is not only driven by three burst base addresses, but also by linear or interleaved orders. The user may also choose to change the burst length from eight 36-bit words to four 36-bit words in a single command. The memory design has to be able to process the changes of burst length, burst order and burst base addresses and provide the fastest possible data latency.
SUMMARY OF THE INVENTION
Increasing the data rate of cache memory while providing the fastest possible data latency improves the overall computer system performance. Using DRAM memory over SRAM has a 4× improvement in density, but a similar 4× decrease in DRAM random cycle-time. The DRAM data rate, however, can be made as fast as the SRAM's by increasing the burst length from two to eight. The increase in burst length adds significant on-chip design complexity and latency. This arises from having to prioritize eight 36-bit data words so that the specified burst exit order is maintained. The present invention is directed to a technique that simplifies the bursting operation so that latency is improved and design complexity is minimized.
The present invention comprises a memory system which can be incorporated in a fast DRAM chip. The memory system includes an array of addressable memory cells, decoding circuitry for selecting n memory bits of data, means for latching said n memory bits of data and finally, bursting the n memory bits of data in any specified burst length and burst order in accordance to the captured memory commands and burst base addresses in the specified cycle.
A first embodiment of this invention is a memory array with a wide I/O architecture with multiple subarrays that can be decoded by subarray addresses. The subarrays have an array of wordlines and bitlines. The wordlines of the subarrays are decoded by wordline addresses at the same time a subarray is decoded by subarray addresses. The columns are mapped into eight sections; each column section having a subset of bitlines that are decoded with bitline addresses at the same time a wordline and a subarray is decoded. Each column section has a fixed burst base-address memory allocation. When writing to column sections, data is formatted according to the burst base address prior to being written into the array. In this manner, column sections are updated in the correct fixed addressing order.
A second embodiment of this invention is a method for reading the memory array. During a read operation, a subarray, a wordline within a subarray and one bitline within each column of the decoded subarray are decoded. Data is accessed from each of the eight column sections which have a fixed burst base-address memory allocation. The exit order of the accessed data is specific to the burst base-addresses captured by the memory at the same time subarray, wordline and bitline addresses are captured. The exit order is also specific to a linear or interleaved burst order control pin, and finally, the exit order is also specific to either a burst of four words or a burst of eight words. The embodiment is a method for a burst of data to exit the chip with the minimum latency and simplest on-chip implementation.
These and other features and advantages of this invention will become apparent from the following detailed description of the presently preferre

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