Reduced latency FIFO

Multiplex communications – Pathfinding or routing – Store and forward

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C370S401000, C370S412000, C710S052000, C710S057000

Reexamination Certificate

active

10158337

ABSTRACT:
A First-In-First-Out (FIFO) block to buffer a packet having a size is presented. The FIFO block includes a receiver to receive a data frame including the packet and overhead information, and to extract the packet from the data frame. A buffer has a plurality of memory locations to store the packet in a FIFO configuration. A buffer manager, in response to detecting a buffer low packet condition, stalls reads of the packet from the buffer.

REFERENCES:
patent: 5959994 (1999-09-01), Boggs et al.
patent: 6195332 (2001-02-01), Tang
patent: 6195346 (2001-02-01), Pierson, Jr.
patent: 6654383 (2003-11-01), Haymes et al.
patent: 7127653 (2006-10-01), Gorshe
patent: 2001/0017723 (2001-08-01), Chang et al.
patent: 2003/0058894 (2003-03-01), Feuerstraeter et al.
patent: 2003/0189925 (2003-10-01), Wellbaum et al.
patent: 2003/0217215 (2003-11-01), Taborek et al.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Reduced latency FIFO does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Reduced latency FIFO, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Reduced latency FIFO will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3927433

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.