Reduced latchup in precharging I/O lines to sense amp signal lev

Details Reduced latchup in precharging I/O lines to sense amp signal lev Reduced latchup in precharging I/O lines to sense amp signal lev

1988-07-22

1990-10-09

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307565, 307530, 365203, H03K 1716, H03K 19003

Patent

active

049623265

ABSTRACT:
I/O lines on a CMOS circuit are precharged to preferred voltage levels in order to avoid latch up. The precharging is achieved by using N channel transistors to provide a precharge which is at a threshold voltage (V.sub.T) below bias voltage V.sub.CC, or (V.sub.CC -V.sub.T). This results in a lower forward bias when V.sub.CC bumps down after the I/O lines are floated. By lowering the precharge voltage by a level corresponding to a threshold voltage (V.sub.T), the allowed range of power supply voltage bumping is increased by this amount. This eliminmates the destructive effect of a negative bump of V.sub.BE, which would have presented a diode forward bias condition. Instead, the power supply may bump to (V.sub.BE +V.sub.T).

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