Reduced instruction set computing apparatus and methods

Details Reduced instruction set computing apparatus and methods Reduced instruction set computing apparatus and methods

1990-03-30

1991-02-12

Fleming, Michael R.

Boots, shoes, and leggings

36423223, 3642323, 3642402, G06F 940

Patent

active

049929348

ABSTRACT:
A reduced instruction set computer (RISC) with a Harvard architecture is disclosed. The RISC may be designed to be used simply as a RISC or may be designed to be used to emulate a complex instruction set computer (CISC). Or, it may be designed for use as either. A CISC design methodology is disclosed whereby a RISC is designed and fabricated and whereby RISC emulation code is written concurrently with design and fabrication and also subsequent to fabrication.

REFERENCES:
patent: 4434462 (1984-02-01), Guttag et al.
patent: 4498135 (1985-02-01), Caudel
patent: 4514801 (1985-04-01), Caudel et al.
patent: 4514805 (1985-04-01), McDonough et al.
patent: 4569016 (1986-02-01), Hao et al.
patent: 4577282 (1986-03-01), Caudel et al.
patent: 4587612 (1986-05-01), Fisk et al.
patent: 4589065 (1986-05-01), Auslander et al.
patent: 4589087 (1986-05-01), Auslander et al.
patent: 4608634 (1986-08-01), Caudel et al.
patent: 4638426 (1987-01-01), Chang et al.
patent: 4719568 (1988-01-01), Carrubba et al.
patent: 4727480 (1988-02-01), Albright et al.
A VSLI RISC, by Patterson et al, IEEE Computer, Sep. 1982, pp. 8-18.
The 801 Minicomputer, by Radin, IBM J. Res. Develop., vol. 27, No. 3, May 1983, pp. 237-246.
Byington, L., Theis, D., "Air Force Standard 1750A ISA Is the New Trend", IEEE Computer, Nov. 1986, pp. 50-59.
"Keeping an Eye on a Circuit Explosion", Electronic Design, Oct. 30, 1986.
Tabak, D., "Which System Is a RISC?", IEEE Computer, Oct. 1986, pp. 85, 86.
Fox, E. R., Kiefer, K. J., Vangen, R. F., Whalen, S. P., "Reduced Instruction Set Architecture for a GaAs Microprocessor System", IEEE Computer, Oct. 1986, pp. 71-81.
Rasset, T. L., Niederland, R. A., Lane, J. H., Geideman, W. A., "A 31-bit RISC Implemented in Enhancement-Mode JFET GaAs", IEEE Computer, Oct., 1986, pp. 60-68.
Meng, "Airborne Architecture Standard Holds On", Digital Design, Oct. 1986, pp. 24, 25.
Silvey, A., Milutinovic, Mendoza-Grado, V., "A Survey of Advanced Microprocessors and HLL Computer Architectures", IEEE Computer, Aug. 1986, pp. 72-85.
Colwell, R. P., Hitchcock, III, C. Y., Jensen, E. D., Sprunt, H. M. Brinkley, Kollar, C. P., "Computers, Complexity, and Controversy", IEEE Computer, Sep. 1985, pp. 8-19.
Ohr, S., "RISC Machines", Electronic Design, Jan. 10, 1985, pp. 175-190.
Patterson, D. A., "Reduced Instruction Set Computers", Communications of the ACM, Jan. 1985, vol. 28, No. 1, pp. 8-21.
Hennesy, J. L., "VLSI Processor Architecture", IEEE Transactions on Computers, vol. C-33, No. 12, Dec. 1984, pp. 1221-1245.
Ungar, D., Blau, R., Foley, P., Samples, D., Patterson, D., "Architecture of SOAR: Smalltalk on a RISC", 11th Annual Symposium on Computer Architecture, Jun. 4-7, 1984, Ann Arbor, Mich.
Wulf, W. A., "Compilers and Computer Architecture", IEEE Computer, Jul. 1981, pp. 41-47.

Affiliated with

Also associated with

Rating

Reduced instruction set computing apparatus and methods does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Reduced instruction set computing apparatus and methods, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Reduced instruction set computing apparatus and methods will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-24931