Reduced instruction set computer system including apparatus and

Details Reduced instruction set computer system including apparatus and Reduced instruction set computer system including apparatus and

1992-07-10

1994-05-31

Dixon, Joseph I.

Boots, shoes, and leggings

395500, 364DIG1, G06F 1300, G06F 1323

Patent

active

053177150

ABSTRACT:
Methods and apparatus are disclosed for transferring data to and from the Local Bus of a reduced instruction set computer (RISC) system, to which a first set of high performance devices, including at least one central processor ("CPU"), is attached, and a Remote Bus, to which a second set of relatively lower performance devices is attached, in a manner that does not limit the RISC processor's performance. According to the preferred embodiment of the invention, a RISC architecture is disclosed that includes a novel data transfer controller ("DTC"), or set of DTCs, suitable for performing the aforesaid data transfer function between the high performance Local Bus and one or more Remote Buses to which complete subsystems or peripherals, typically having different (and lower) performance characteristics, are attached. The resulting RISC arthitecture permits commercially available peripherals and subsystems to be used with high performance RISC processors without limiting RISC system performance.

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