Reduced impact power up/down mode in electrical circuits

Electrical transmission or interconnection systems – Plural load circuit systems – Selectively connected or controlled load circuits

Reexamination Certificate

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Reexamination Certificate

active

06239510

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to electrical circuits, in particular, an apparatus for controlling variations in a voltage signal supplied to an electrical circuit.
DESCRIPTION OF THE RELATED ART
Most electrical circuits produced today are fabricated on a single substrate known as an integrated circuit (IC) chip. These IC chips are often interconnected via further substrates, such as printed circuit boards. The IC chips are typically connected to each other by metal traces formed on the surface of the circuit boards. The IC chips may include active devices such as logic circuitry or memory cells. The plurality of IC chips on the circuit board are typically controlled by a microprocessor or central processing unit (CPU) which may or may not be disposed on the board. The circuit board also usually includes a clock generator and a voltage source, both of which may alternatively be located off circuit board. The clock generator and the voltage source produce signals which are applied to the IC chips to make them operate. The IC chips along with the CPU and other associated discrete circuit elements form a circuit device for effecting a particular task.
While the circuit device is operating, various IC chips may be active at different times. Thus, some chips are “on” while others are “off.” Typically, a single voltage source provides power to all the IC chips on a given circuit board. In order to conserve power, the CPU often turns “off” IC chips which are not presently needed. Typically, the IC chip is switched “off” by stopping a clock signal (produced by the clock generator) to the device, rather than removing the voltage signal supplied by the voltage source. When these chips (i.e. those switched “off”) are needed again by the device, they are switched back “on” by the CPU, by reapplication of the clock signal. Each time an IC chip is turned “on” or “off” by the CPU, the voltage source must compensate for the increasing and decreasing load. In order to accomplish this, the voltage source includes a feedback loop which serves to keep the voltage signal at a constant level no matter what the load. However, the constant adding and removing of loads from the voltage source causes variations in the voltage signal during the transition time between “on” and “off” states. These variations in the voltage signal can lead to malfunctions in the circuit device.
FIG. 1
shows an exemplary circuit device
10
. The device
10
includes a substrate
15
with IC chips
20
,
25
,
30
, and
35
attached thereto. The circuit device
10
also includes a CPU
40
for controlling the operations of the chips
20
-
35
. The chips
20
-
35
are connected to the CPU
40
and to the other chips by metal traces (not shown) formed on the substrate
15
. When the CPU
40
determines that one of the chips
20
-
35
is not presently needed for operation of the circuit device
10
, the CPU issues a command which removes the clock signal from the particular chip. When the particular chip is again required by the circuit device
10
, the CPU issues a command which returns the clock signal to the particular device. When a device is turned “on” or “off” by the CPU
40
, a large variation in the supply voltage occurs as shown in FIGS.
2
(
a
) and
2
(
b
), explained in detail below.
FIG.
2
(
a
) shows a typical voltage signal during the “power down” (i.e. turning “off”) of one of the chips
20
-
35
of the circuit device
10
. Note that at the time the particular chip (e.g. chip
20
) is powered down, time T
0
in the figure, the voltage supply signal V
dd
experiences a rise due to the decreased load. This higher than normal supply voltage can cause significant damage to the other chips (e.g. chips
25
-
35
) of the circuit device
10
. FIG.
2
(
b
) shows a typical voltage signal during the “power up” (i.e. turning “on”) of one of the chips
20
-
35
of the circuit device
10
. Note that at the time the particular chip (e.g. chip
20
) is powered up, time T
0
in the figure, the voltage supply signal V
dd
experiences a fall due to the increased load. This variation in the voltage signal can cause various problems for the circuit device
10
. In particular, each circuit device
10
has a threshold voltage V
T
which protects the device from undervoltage conditions. If the supply voltage for the circuit device
10
falls below this value V
T
, the entire device will reset. Often, a variation due to the addition of a load causes the supply voltage signal V
dd
to dip below the V
T
level as shown in the figure. This causes the circuit device
10
to reset even though no reset was intended.
In order to solve the above problems, capacitors are often connected externally of the circuit device
10
. These capacitors are typically large capacitance elements which significantly reduce the variations in the supply voltage signal. However, in many applications, there is insufficient room to add large external capacitors. For instance, in a pacemaker system, the only elements which may be used are a device and a battery. Therefore, there is currently a need for an apparatus for controlling variations in a voltage supply signal which can integrated with a device.
SUMMARY OF THE INVENTION
The present invention is an apparatus for reducing variations in a supply voltage signal of a circuit including an actual load. The variations are reduced by adding at least one redundant load to the circuit. An electrical signal for operating the different devices of the circuit is applied to both the redundant load(s) and actual load at different times during the operation of the circuit. The electrical signal is applied to the redundant load(s) when the actual load is not operating and is removed when the actual load is operating. The substitution of redundant load(s) for the actual load is performed by a controller. The adding and removing of loads from the electrical signal causes variations in the supply voltage for the circuit to be minimized.


REFERENCES:
patent: 3770977 (1973-11-01), Mcintosh
patent: 3980943 (1976-09-01), Cailleux et al.
patent: 4890212 (1989-12-01), Kumon et al.
patent: 5172008 (1992-12-01), Odagiri
patent: 5943278 (1999-08-01), Su

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