Reduced hot carrier induced parasitic sidewall device...

Details Reduced hot carrier induced parasitic sidewall device... Reduced hot carrier induced parasitic sidewall device...

2005-03-15

2005-03-15

Prenty, Mark V. (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including dielectric isolation means

C257S514000, C257S515000, C257S404000

Reexamination Certificate

active

06867472

ABSTRACT:
A semiconductor device includes a transistor junction formed in a substrate adjacent to an isolation region. A region between the transistor junction and the isolation region includes an area susceptible to hot carrier effects. The transistor junction extends from a surface of the substrate to a first depth. A buried conductive channel layer is formed within the transistor junction between the surface of the substrate and the first depth. The buried conductive channel layer has a peak conduction depth, which is different from a depth of the area susceptible to hot carrier effects.

REFERENCES:
patent: 4885617 (1989-12-01), Mazure-Espejo et al.
patent: 5940717 (1999-08-01), Rengarajan et al.
patent: 6140208 (2000-10-01), Agahi et al.
patent: 6521493 (2003-02-01), Alsmeier et al.
patent: 6747318 (2004-06-01), Kapre et al.

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