Reduced field implant for dynamic memory cell array

Details Reduced field implant for dynamic memory cell array Reduced field implant for dynamic memory cell array

1980-03-21

1983-06-14

Roy, Upendra

Metal treatment

Compositions

Heat treating

29571, 29576B, 148187, 357 23, 357 91, H01L 21263, G11C 1140, G11C 1700

Patent

active

043881211

ABSTRACT:
A dynamic read/write memory cell of the one-transistor N-channel silicon gate type is made by a double-level polysilicon process in which the implant dosage is reduced for the channel stop regions beneath the field oxide. This causes the signal level on the bit lines to be improved, and also reduces leakage problems.

REFERENCES:
patent: 3996658 (1976-12-01), Takei et al.
patent: 4033026 (1977-07-01), Pashley
patent: 4055444 (1977-10-01), Mohan Rao
patent: 4125933 (1978-11-01), Baldwin
patent: 4140547 (1979-02-01), Shibata et al.
patent: 4145803 (1979-03-01), Tasch, Jr.
patent: 4230504 (1980-10-01), Kuo
patent: 4240092 (1980-12-01), Kuo
patent: 4240195 (1980-12-01), Clemens et al.
patent: 4258466 (1981-03-01), Kuo et al.
patent: 4277882 (1981-07-01), Crossley
patent: 4280271 (1981-07-01), Lou et al.
Sakamoto et al. Jap. Jour. Appl. Phys. 18 (1979) Suppl. 18-1, pp. 85-91.

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