Reduced error asynchronous clock

Details Reduced error asynchronous clock Reduced error asynchronous clock

1999-10-07

2001-03-20

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S160000, C327S295000, C327S271000, C327S278000

Reexamination Certificate

active

06204711

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to electronic timers and, more particularly, to an improved asynchronous clock for processing signals from random events.
BACKGROUND ART
In many electronic applications, it is necessary to process signals from random events. For example, signals generated by gamma rays in medical imaging equipment are random events. To produce images or data from such events, several process steps must occur at specific time intervals after an event detection. Typically, this consists of several sequential steps whose timing (start and duration) must be precisely controlled. The timing of the control signals for the processing hardware is typically derived from the start of the event signal.
In the current art, these control signals are typically generated using cascaded delays, multi-tap delays, or a multivibrator with a constant period. Each of these methods are described below, with reference to an integrator. An integrator requires a control signal to begin integration, and another control signal to reset. An integration step is a common step in the processing of medical images. Of course, many other signals may be necessary but, for the sake of brevity, will not be used in this discussion. In addition, the timing of each control signal depends on the individual application as well.
In the case where the control signals are generated with a series of cascaded delays, (typically digital delay lines) an input pulse representing the start of the event signal is communicated to a delay, and starts the integration. The output of the delay stops the integration, initiates the measurement of the integrated value, and is communicated to a second delay. The output of the second delay starts the reset of the integrator, and is also communicated to a third delay. The output of the third delay terminates the reset of the integrator, and so on.
The cascaded delay line method of generating control signals has several limitations. First, each control signal requires its own delay line. Therefore, systems requiring many signals must have many delay lines. This increases the system cost and power consumption. Second, in general, it is desirable to implement control logic using programmable devices such as PLDs. Cascaded delay lines, however, require a large number of I/O connections to the PLD for the delays. The large number of connections requires the use of larger PLDs (more pins) than necessary. Third, the increased number of devices and connections reduces the reliability of the circuit.
In the case where the control signals are generated with a multi-tap delay, the device has a fixed total delay, with a series of outputs providing access to the signal at equal timing intervals as it propagates through the total delay. An input pulse representing the start of the event signal is fed into the delay, and starts the integration. When the signal appears on a selected tap, the integration is stopped and the measurement of the integrated value is initiated. When the signal appears on a second selected tap, the reset of the integrator commences. The reset is terminated when the signal appears on a third selected tap and so on.
The multi-tap delay line method also has several limitations. In particular, each control signal requires its own tap on the delay line. Therefore, systems requiring more control signals than taps on a delay line require multiple delay lines, increasing the system cost and power consumption. Furthermore, generally it is desirable to implement control logic using programmable devices such as PLDs. Like the case with cascaded delay lines, this method requires a large number of I/O connections which requires the use of larger PLDs than necessary. In addition, multi-tap delay lines require that the input pulse's duration be long (i.e., 40% of the total delay time), and the minimum time between input pulses must be four times the pulse duration. This leads to long “dead” times in the control circuit. A further drawback is that multi-tap delay lines, in general, have poor timing accuracy compared with single delay lines.
A string of clock pulses can also be generated using a multivibrator, which is triggered by the start of the event signal. The clock pulses from the multivibrator are fed to a control circuit. This control circuit generates the signals which start and stop the integrator, the measuring period, and the reset cycle, based upon the number of clock pulses received. At the end of the reset cycle, the multivibrator is stopped.
The multivibrator method, however, also has limitations. For example, the control signal can be generated only on the leading edge or trailing edge of the multivibrator clock. Therefore, timing between control signals is a multiple of one half of a clock cycle. For a given total delay, a smaller clock period requires more clock cycles. The accuracy of each clock period is dependent upon the accuracy of the delay line (if used) and the variation in the propagation delay through the clock's logic circuit. Therefore, a larger number of clock cycles will result in larger timing errors. This error can be reduced by using larger delay lines, i.e., a longer period clock. However, for the multivibrator to settle in its steady state, an integer number of full clock cycles is required for the clock system to be cleared and ready for a new start pulse. This results in additional dead time if the required delay is not an integer multiple of a full cycle. For example, a clock using 75 ns-delay line is disabled by the control logic on the clock's falling edge. The clock is at the correct start point, but the delay line requires 75 ns before it is cleared. If the clock is started during that period, the clock will not function correctly.
Accordingly, there is a need for an improved asynchronous clock having reduced error as compared to conventional timing methods and systems.
SUMMARY OF THE INVENTION
The present invention overcomes the drawbacks of these prior art systems through the provision of a cascaded delay asynchronous clock (CDAC) for operating control logic to process an event signal. The clock comprises a flip-flop for receiving the event signal and generating a clock enable signal and a logic gate connected to the flip-flop for receiving the clock enable signal and generating a clock signal. The clock signal is then communicated to the control logic for use in the control process. The CDAC further includes a plurality of cascaded delays connected in series, such that the first of cascaded delay is connected to receive as an input the clock signal, and the last delay is further connected to the logic gate. The output of each of the plurality of delays is fed back to the control logic to generate timing signals.
In another aspect of the present invention, a variable duty cycle asynchronous clock (VDAC) for operating control logic to process an event signal is disclosed. The clock comprises a first flip-flop for receiving the event signal and generating a clock enable signal, decode logic adapted to receive the clock enable signal and generate a control signal, and a second flip-flop adapted to receive the control signal and generate a clock signal. The clock signal is communicated to the control logic for use as a timing signal. The VDAC further includes first and second series connected delays, wherein the output of each of the delays is fed back to the decode logic and control logic to generate timing signals.
The present invention includes the advantages associated with cascaded delay lines and multivibrators without the associated drawbacks. Other objects and advantages of the invention will become apparent upon reading the following detailed description and appended claims and upon reference to the accompanying drawings.


REFERENCES:
patent: 5740410 (1998-04-01), McDermott

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