Reduced delay circuits for shift register latch scan strings

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H04B 1700

Patent

active

051503662

ABSTRACT:
Delays in critical signal paths are eliminated in circuits employing level sensitive scan design methods for implementing self-test operations. In particular, scan strings associataed with primary input lines are segregated and supplied to a separate distinct signature register so as to permit simplified degating circuitry on the input side of those shift register latches which are in fact associated with primary input signal lines.

REFERENCES:
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patent: 4860290 (1989-08-01), Daniels et al.
patent: 4897837 (1990-01-01), Ishihara et al.
patent: 5032783 (1991-07-01), Hwang et al.
patent: 5043985 (1991-08-01), Lin et al.
patent: 5043986 (1991-08-01), Agrawal et al.

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