Reduced delay circuits for shift register latch scan strings

Details Reduced delay circuits for shift register latch scan strings Reduced delay circuits for shift register latch scan strings

1990-08-01

1992-09-22

Smith, Jerry

Excavating

H04B 1700

Patent

active

051503662

ABSTRACT:
Delays in critical signal paths are eliminated in circuits employing level sensitive scan design methods for implementing self-test operations. In particular, scan strings associataed with primary input lines are segregated and supplied to a separate distinct signature register so as to permit simplified degating circuitry on the input side of those shift register latches which are in fact associated with primary input signal lines.

REFERENCES:
patent: 4710933 (1987-12-01), Powell et al.
patent: 4780666 (1988-10-01), Sakashita et al.
patent: 4860290 (1989-08-01), Daniels et al.
patent: 4897837 (1990-01-01), Ishihara et al.
patent: 5032783 (1991-07-01), Hwang et al.
patent: 5043985 (1991-08-01), Lin et al.
patent: 5043986 (1991-08-01), Agrawal et al.

Affiliated with

Also associated with

Rating

Reduced delay circuits for shift register latch scan strings does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Reduced delay circuits for shift register latch scan strings, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Reduced delay circuits for shift register latch scan strings will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1075171