Reduced data line pre-fetch scheme

Details Reduced data line pre-fetch scheme Reduced data line pre-fetch scheme

2006-11-28

2006-11-28

Nguyen, Tuan T. (Department: 2824)

Static information storage and retrieval

Interconnection arrangements

C365S189050, C365S198000, C710S305000, C710S300000, C712S033000

Reexamination Certificate

active

07142443

ABSTRACT:
A memory device for reducing the number of data read lines needed in a memory device. Specifically, multiple helper flip-flops are used to prefetch data in a memory device. The helper flip-flops are configured to latch one or two of the data bits from a 4-bit prefetch in an alternating periodic fashion, thereby necessitating fewer data lines.

REFERENCES:
patent: 4014006 (1977-03-01), Sorensen et al.
patent: 4947373 (1990-08-01), Yamaguchi et al.
patent: 5006980 (1991-04-01), Sanders et al.
patent: 5325330 (1994-06-01), Morgan et al.
patent: 5463582 (1995-10-01), Kobayashi et al.
patent: 5559969 (1996-09-01), Jennings et al.
patent: 6026050 (2000-02-01), Baker et al.
patent: 6166942 (2000-12-01), Vo et al.
patent: 6704828 (2004-03-01), Merritt et al.
patent: 2002/0021613 (2002-02-01), Yamauchi

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