Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
1999-05-20
2001-05-29
Tran, Minh Loan (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S691000, C257S781000, C257S698000, C257S738000, C257S778000, C257S780000, C257S774000, C361S794000, C361S795000
Reexamination Certificate
active
06239485
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integrated circuit device packaging, and more specifically, to an interposer substrate capable of reducing cross-talk between signal lines which is suitable for interconnecting integrated circuit chips to a printed circuit board or other substrate.
2. Description of the Prior Art
An interposer is a structure used in the manufacture of single and multi-chip modules (SCMs or MCMs) to electrically connect one or more integrated circuit chips (ICs) to a printed circuit board or other substrate. The interposer provides power and ground connections between the board or substrate and the ICs. The interposer also provides signal paths between the IC chips and the board or substrate, and if desired, between different chips mounted on the interposer. An interposer thus provides a means of interconnecting signal, power, and ground lines between a substrate, an integrated circuit chip or chips, and ultimately a package containing the chip(s).
As the number of components in electronic devices increases and the size of the individual components decreases, there is an increase in the number and density of power, ground, and signal interconnections needed between individual ICs and the substrate to which the chips are connected. This means that the density of the interconnections which need to be included as part of an interposer also increases. However, problems arise in placing signal lines in close proximity to each other and to power supply lines when fabricating such an interposer. These problems include interference and cross-talk arising from coupling between the lines on a common layer or between signal lines on different signal layers, and capacitive coupling between the lines and the substrate which produces noise in the signals. In conjunction with the separation between the various lines, the dielectric constant of the substrate material thus plays an important role in reducing (or creating) these type of problems.
Another disadvantage of conventional approaches to packaging IC chips in MCMs arises from the method used to deliver power to the chips. This problem results because power lines are typically routed through the same substrate which is utilized to carry signals to and from the chip. The power feedthroughs will compete for space with the signal I/O lines. This will further increase the problems caused by densely packed signal traces. Another important disadvantage is that the thinness of the substrates used in traditional multichip modules results in the power feeds to the IC chips having a relatively high impedance. This results in undesired noise, power loss, and excess thermal energy production. These problems are relevant to the routing of both power and signal lines though an interposer substrate.
What is desired is an interposer for interconnecting a single integrated circuit chip to a substrate, or for interconnecting a plurality of chips to each other and to a substrate, which addresses the noted disadvantages of conventional structures.
SUMMARY OF THE INVENTION
The present invention is directed to an interposer for providing power, ground, and signal connections between an integrated circuit chip or chips and a substrate. The inventive interposer includes a signal core and external power/ground connection wrap. The two sections may be fabricated and tested separately, then joined together using z-connection technology. The signal core is formed from a conductive power/ground plane positioned between two dielectric layers. A patterned metal layer is formed on each dielectric layer. The two metal layers are interconnected by a through via or post process. The conductive power/ground plane functions to reduce signal cross-talk between signal lines formed on the two patterned metal layers.
The power/ground wrap includes an upper substrate positioned above the signal core and a lower substrate positioned below the signal core. The upper and lower substrates of the power/ground wrap are formed from a dielectric film having a patterned metal layer on both sides, with the patterned layers connected by a through via or post process. The two power/ground wrap substrates may be formed separately or from one substrate which is bent into a desired form (e.g., a “U” shape). The two power/ground substrates are maintained in their proper alignment relative to the signal core and to each other by edge connectors which are also connected to the signal core's intermediary power/ground plane.
The top layer of the upper power/ground wrap substrate and the bottom layer of the lower power/ground wrap substrate serve as the ground layer. The ground layer includes isolated pads for signal and power interconnections between the base substrate on which the interposer is mounted and the chip(s) mounted on top of the interposer. The bottom layer of the upper substrate and the top layer of the lower substrate of the power/ground wrap serve as the power layer and include isolated pads for signal interconnections. With an integrated circuit chip or chips connected to the upper layer of the top substrate of the power/ground wrap and a printed circuit board or other mounting substrate connected to the bottom layer of the lower substrate of the wrap, the inventive interposer provides a set of high density and electrically isolated signal, power, and ground interconnections having reduced cross-talk between signal lines.
REFERENCES:
patent: 4202007 (1980-05-01), Dougherty et al.
patent: 4271588 (1981-06-01), Nowak
patent: 4547834 (1985-10-01), Dumont et al.
patent: 4597029 (1986-06-01), Kucharek et al.
patent: 4600970 (1986-07-01), Bauer
patent: 4601526 (1986-07-01), White et al.
patent: 4672152 (1987-06-01), Shinohara et al.
patent: 4706165 (1987-11-01), Takenaka et al.
patent: 4736276 (1988-04-01), Ushifusa et al.
patent: 4821142 (1989-04-01), Ushifusa et al.
patent: 4854038 (1989-08-01), Wiley
patent: 4884170 (1989-11-01), Ohki et al.
patent: 4922377 (1990-05-01), Matsumoto et al.
patent: 4926241 (1990-05-01), Carey
patent: 4931134 (1990-06-01), Hatvervitz
patent: 4984132 (1991-01-01), Sakurai et al.
patent: 5012047 (1991-04-01), Dohya
patent: 5036431 (1991-07-01), Adachi et al.
patent: 5097393 (1992-03-01), Nelson et al.
patent: 5142448 (1992-08-01), Kober et al.
patent: 5159530 (1992-10-01), Komoto
patent: 5264729 (1993-11-01), Rostoker et al.
patent: 5281151 (1994-01-01), Arima et al.
patent: 5325268 (1994-06-01), Nachnani et al.
patent: 5331514 (1994-07-01), Kuroda
patent: 5354955 (1994-10-01), Gregor et al.
patent: 5362656 (1994-11-01), McMahon
patent: 5367435 (1994-11-01), Andros et al.
patent: 5375042 (1994-12-01), Arima et al.
patent: 5386341 (1995-01-01), Olson et al.
patent: 5394303 (1995-02-01), Yamaji
patent: 5396034 (1995-03-01), Fujita et al.
patent: 5418689 (1995-05-01), Alpaugh et al.
patent: 5419038 (1995-05-01), Wang et al.
patent: 5426563 (1995-06-01), Moresco et al.
patent: 5428190 (1995-06-01), Stopperan
patent: 5435733 (1995-07-01), Chernicky et al.
patent: 5448020 (1995-09-01), Pendse
patent: 5450290 (1995-09-01), Boyko et al.
patent: 5477933 (1995-12-01), Nguyen
patent: 5479110 (1995-12-01), Crane et al.
patent: 5491612 (1996-02-01), Nicewarner, Jr.
patent: 5530288 (1996-06-01), Stone
patent: 5534666 (1996-07-01), Ishida
patent: 5544017 (1996-08-01), Beilin et al.
patent: 5708568 (1998-01-01), Ostendorf
patent: 5719749 (1998-02-01), Stopperan
patent: 5789815 (1998-08-01), Tessier et al.
patent: 5854534 (1998-12-01), Beilin et al.
patent: 0506225 A2 (1992-09-01), None
patent: 0506225 A3 (1992-09-01), None
Craig N. Ernsberger et al. FLEXCON ™ '96, “Colaminated Multilayer Flip Chip T-BGA Package Development” 29-43.
Sarah E. Leach et al. 1997 International Symposium on Advanced Packaging Materials, “Colamination Technology for electronic Packaging Applications” 38-41.
Catherine Gallagher et al. 1997 International Symposium on Advanced Packaging Materials, “Vertical Interconnect in Multilayer Applications Using Ormet® Conductive Composites” 35-37.
Ernsberger Proceedings of the F
Beilin Solomon
Chou William
Lee Michael G.
Peters Michael G.
Takahashi Yasuhito
Brothers Coudert
Fujitsu Limited
Thai Luan
Tran Minh Loan
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