Reduced cost, high speed circuit test arrangement

Details Reduced cost, high speed circuit test arrangement Reduced cost, high speed circuit test arrangement

2000-08-08

2003-06-24

Cuneo, Kamand (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S755090

Reexamination Certificate

active

06583639

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to an integrated circuit test arrangement and more particularly to an integrated circuit test arrangement for testing at very high clock rates.
BACKGROUND OF THE INVENTION
During the fabrication of integrated circuit devices, those devices are produced in quantity on a large silicon wafer substrate. Individual integrated circuit devices are sliced from the large silicon wafer. Each resulting individual device is a unique chip with a purpose defined by a device specification. There is a possibility of failure of the individual device to function in accordance with is specification. To identify such devices, a series of tests are run on the device to verify that the device meets its specification. The device under test may be a microprocessor, a memory device, or a module.
Integrated circuit testing today uses testing arrangements and procedures which are very similar to those that were used some fifteen years ago. A large box of electronics, or tester, includes tester logic with drivers and clock edge controllers. Outputs of the drivers are connected through coaxial cables to device sockets mounted on a test board. For testing the integrated circuit devices are inserted into the sockets. Testing several devices at once under control of a single tester saves tester time. This is important because testers each cost some two million dollars.
A typical tester includes a central processing unit which controls several algorithm generators that are electrically inter connected with registers. These registers output data to the devices under control of edge controllers which assure exact timing of data pulses. The central processing unit has full programming capability for running desired tests on the devices. There are sufficient memory, hard disk, monitor, and entry systems for performing tests on several integrated circuits in parallel. The tester drivers are inter connected with level translator through a cable which may be several decimeters long. Such level translators are inter connected with the sockets on the test board through another cable that also may be several decimeters long.
When the tester is operating at 10 MHz, the interconnection cable lengths are not critical. For instance, a coaxial cable that differs in length by approximately three centimeters causes a difference of 100 picoseconds in a time slot of 100 nanoseconds and is negligible or meaningless in regard to most, if not all, testing.
Depending upon the device being tested, the tests may be performed before or after assembly into a package. Some are tested both before and after assembly. The tests are of various types. A power test verifies that the device does not burn up because of a short circuit or other low impedance fault. A functionality test verifies that the device functions in accordance with the device specification. A speed test verifies that the device operates at its specified speed. Also inputs from external sources, timings, and bias voltages are varied to determine whether or not the device tolerates deviations allowed by the device specification.
Currently, existing testers are being adjusted to run tests at higher and higher speeds. Every time the clock speed is increased by more than approximately twenty percent above a prior test speed, a new upgraded tester must be used. This requires a costly, and undesirable replacement investment.
Newly designed devices are operating with a 250 MHz clock and a time slot of four nanoseconds. There is a one nanosecond set up and hold time. The previously mentioned difference in cable length of three centimeters causing the 100 picosecond difference is approximately ten percent of the time slot and is very significant.
In the near future, devices will be operating even faster with a time slot of two nanoseconds. Then the cable length difference will cause a change of twenty to twenty-five percent of the time slot. That much of a change is critical to whether or not the devices can be effectively tested. This is a problem that needs a solution to both the timing issue and the cost of replacement testers.
SUMMARY OF THE INVENTION
These problems and others are resolved by an integrated circuit device test arrangement that includes a plurality of microcomputer. Each of the microcomputers is interconnected directly through a separate test socket to a separate integrated circuit device that is inserted into the test socket. A device tester is coupled to the plurality of microcomputers for transmitting information between the device tester and the plurality of microcomputers. Each microcomputer contains instructions and data for performing a test routine on the associated integrated circuit device and transmitting selected results of the test routine to the tester.


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