Reduced complexity primary and secondary synchronization...

Details Reduced complexity primary and secondary synchronization... Reduced complexity primary and secondary synchronization...

2006-05-02

2006-05-02

Tran, CongVan (Department: 2683)

Multiplex communications

Communication over free space

Combining or distributing information via code word channels...

C370S335000, C370S441000, C370S503000, C375S143000, C375S150000

Reexamination Certificate

active

07039036

ABSTRACT:
A circuit for processing binary sequences is designed with a plurality of stages (530–534) coupled to provide plural signal paths (526,528). Each stage includes respective signal paths (550,562) for a first Ra1(k) and a second Rb1(k) data sequence. Each stage further includes a respective delay circuit (502) having a different delay from said respective delay circuit of each other stage (504,506) of the plurality of stages. A stage having a greatest delay (502) precedes other stages (504,506) in the plurality of stages of at least one of the plural signal paths.

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