Reduced complexity linear phase detector

Details Reduced complexity linear phase detector Reduced complexity linear phase detector

2003-05-30

2004-10-19

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By phase

C327S012000

Reexamination Certificate

active

06806740

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to electronic circuits, and more particularly to linear phase detectors.
BACKGROUND OF THE INVENTION
Linear phase detectors are commonly utilized in phase-locked loops (PLLs) and other types of clock recovery circuits. Such clock recovery circuits may be implemented in integrated circuits used in a wide variety of electronic systems, including communication systems, interconnection systems and data storage systems.
A well-known type of conventional linear phase detector is the so-called Hogge detector, described in C. R. Hogge, “A Self-Correcting Clock Recovery Circuit,” IEEE Journal of Lightwave Technology, Vol. LT-3, pp. 1312-1314, December 1985, which is incorporated by reference herein. Such a detector generally comprises a pair of flip-flops connected in series and a pair of two-input exclusive-or (XOR) gates, with each of the XOR gates receiving as its two inputs the input and output of a corresponding one of the flip-flops.
An example of a Hogge detector configured for use in a PLL for clock and data recovery in a high speed optical-electrical interconnection system is described in M. Burzio et al., “A high speed 0.7 &mgr;m CMOS PLL circuit for clock/data recovery in interconnection systems,” ESSCIRC '96 Proceedings of the 22nd European Solid-State Circuits Conference, which is incorporated by reference herein.
Conventional Hogge detectors such as those described in the above-cited references suffer from a significant drawback in that these detectors generally include at least two flip-flops that are formed using a total of four latch circuits. This results in undue circuit complexity and power consumption, particularly in integrated circuit applications which may involve many such linear phase detectors.
Other phase detector circuits known in the art are configured to eliminate the use of flip-flops altogether. For example, a phase detector that utilizes delay cells implemented by inverters, and includes no flip-flops, is described in Y. Tang et al., “A non-sequential phase detector for PLL-based high-speed data/clock recovery,” Proceedings of 2000 Midwest Symposium on Circuits and Systems, pp. 428-431, August 2000, which is incorporated by reference herein. However, the problem with these alternative phase detector circuits is that they fail to provide the advantageous linearity commonly associated with the Hogge detector.
A need therefore exists for an improved phase detector which exhibits substantially reduced circuit complexity and power consumption relative to the above-described Hogge detector, while also maintaining similar linearity.
SUMMARY OF THE INVENTION
The present invention provides an improved linear phase detector which in an illustrative embodiment addresses the above-noted need.
In accordance with one aspect of the invention, a linear phase detector includes first, second and third latches connected in series, each of the latches having a data input, a data output and a clock input. The linear phase detector further includes reference signal generation circuitry and error signal generation circuitry. The reference signal generation circuitry has at least a first input coupled to the data output of the second latch and a second input coupled to the data output of the third latch. The error signal generation circuitry has at least a first input coupled to the data input of the first latch and a second input coupled to the data output of the second latch, and is configured to generate an output that is indicative, relative to the reference signal, of phase error of a clock signal.
The linear phase detector is preferably configured such that a first version of the clock signal is applied to the clock inputs of the first and third latches, and a second version of the clock signal is applied to the clock input of the second latch, the first and second versions being complementary relative to one another.
In the illustrative embodiment, the error signal generation circuitry is configured to generate an output error signal comprising one or more pulses each having a pulse width that, relative to a corresponding pulse of the reference signal, is indicative of the phase error of the clock signal. More specifically, the pulse width of a given pulse of the error signal being greater than that of a corresponding pulse of the reference signal indicates a late clock signal condition, the pulse width of the given pulse of the error signal being less than that of the corresponding pulse of the reference signal indicates an early clock signal condition, and the pulse width of the given pulse of the error signal being substantially equal to that of the corresponding pulse of the reference signal indicates a substantially zero phase error condition.
The linear phase detector may be implemented, for example, as a component of a clock recovery circuit, which may be in the form of a portion of an integrated circuit, or in other applications.
Advantageously, a linear phase detector in the illustrative embodiment includes a total of only three latches, and thus exhibits reduced circuit complexity and power consumption relative to the conventional four-latch Hogge detector. Moreover, this illustrative linear phase detector provides substantially the same linearity as the conventional four-latch Hogge detector. Utilization of linear phase detectors in accordance with the present invention can therefore save both area and power in integrated circuit applications.


REFERENCES:
patent: 5027085 (1991-06-01), DeVito
patent: 6463109 (2002-10-01), McCormack et al.
patent: 6590426 (2003-07-01), Perrott
patent: WO 9845949 (1998-10-01), None
M. Burzio et al., “A High Speed 0.7&mgr;m CMOS PLL Circuit for Clock/Data Recovery in Interconnection Systems,” ESSCIRC, '96 Proceedings of the 22nd European Solid-State Circuits Conference, 4 pages, 1996.
C.R. Hogge, “A Self Correcting Clock Recovery Circuit,” IEEE Journal of Lightwave Technology, vol. LT-3, pp. 1312-1314, Dec. 1985.
Y. Tang et al., “A Non-sequential Phase Detector for PLL-based High-Speed Data/Clock Recovery,” Proceedings of 2000 Midwest Symposium on Circuits and Systems, pp. 428-431, Aug. 2000.

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