Reduced column leakage during programming for a flash memory arr

Details Reduced column leakage during programming for a flash memory arr Reduced column leakage during programming for a flash memory arr

1995-04-21

1996-11-26

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular biasing

36518518, 36518530, G11C 1602

Patent

active

055792618

ABSTRACT:
A method for programing a cell in an array of flash memory cells connected to a bit line using hot-electron injection. In the method, a negative word line voltage is applied to unselected cells connected to the bit line to create a negative gate to source voltage in the unselected cells. The negative gate to source voltage in the unselected cells is provided to prevent overerased cells, or cells which have a negative threshold, from turning on to reduce bit line leakage current.

REFERENCES:
patent: 5293212 (1994-03-01), Yamamoto
patent: 5396459 (1995-03-01), Arakawa
patent: 5408429 (1995-04-01), Sawada
patent: 5416738 (1995-05-01), Shrivastava
J. Chen, N. Radjy, S. Cagnina and J. Lien, "Study of Over Erase Correction Convergence Point Vth*," Advanced Micro Devices Technology Conference, 1994, pp. 68-69.
S. Yamada, T. Suzuki, E. Obi, M. Oshikiri, K. Naruke and M. Wada, "A Self-Convergence Erasing Scheme For A Simpled Stacked Gate Flash EEPROM," IEEE Tech. Dig. IEDM 1991, pp. 307-310.

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