Reduced circuitry implementation for coverting two equal values

Details Reduced circuitry implementation for coverting two equal values Reduced circuitry implementation for coverting two equal values

1995-02-21

1996-10-08

Malzahn, David H.

Boots, shoes, and leggings

364770, G06F 748, G06F 750

Patent

active

055638147

ABSTRACT:
An apparatus and method for converting equal multi-bit digital values to non-equal multi-bit digital values that differ by one. The apparatus being an electronic circuit incorporated on an integrated chip, the circuit including an input register, a comparator, logic gates, and an output register. The input register receives at least two multi-bit digital values and supplies these values to the comparator. The comparator compares the values and determines if they are equal. The output of the comparator assumes one of either a logic HI or a logic LO state if the digital values are equal and the other of either a logic HI or logic LO state if the digital values are non-equal. The output of the comparator and the least significant bit associated with each of the multi-bit digital values received by the input register are input into the logic gates. In the event the two multi-bit digital values are non-equal, the logic gates pass the values through the circuit and to the output register in an unchanged form. In the event the two multi-bit digital values are equal, the logic gates manipulate the least significant bit of at least one of the multi-bit digital values so as to result in two non-equal values at the output register. According to the method of the invention, only the least significant bit of either of two equal multi-bit digital values will be changed and the resulting non-equal multi-bit digital values will differ by one.

REFERENCES:
patent: 3394249 (1968-07-01), Abernathy et al.
patent: 3989940 (1976-11-01), Kihara
patent: 4417315 (1983-11-01), Russell
patent: 4486851 (1984-12-01), Christopher et al.
patent: 5027310 (1991-06-01), Dalrymple
Elliott, "Increment-Decrement Logic" IBM Technical Disclosure Bulletin vol. 11 No. 3 Aug. 1968 pp. 297-298 364/770.
"Parallel-Array Incrementing Network" IBM Tech. Disclosure Bulletin vol. 27 No. 11 Apr. 1985 pp. 6450-6453 364/770.

Affiliated with

Also associated with

Rating

Reduced circuitry implementation for coverting two equal values does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Reduced circuitry implementation for coverting two equal values , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Reduced circuitry implementation for coverting two equal values will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-62242