Reduced chip testing scheme at wafer level

Details Reduced chip testing scheme at wafer level Reduced chip testing scheme at wafer level

2007-05-15

2007-05-15

Nguyen, Ha Tran (Department: 2829)

Electricity: measuring and testing

Measuring, testing, or sensing electricity, per se

With rotor

C324S765010

Reexamination Certificate

active

10527569

ABSTRACT:
The present invention relates to production testing of semiconductor devices, more specifically to production testing of such devices at wafer level.A method according to the present invention comprises the steps of generating (20) quality test-data at a limited number of semiconductor devices on the wafer, deciding (24) based on the generated quality test-data whether other semiconductor devices on the wafer are to be tested, and based on the result of the deciding step, testing (28) or not testing (26) the other semiconductor devices on the wafer.A corresponding wafer prober is also described.

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patent: 5714888 (1998-02-01), Naujoks
patent: 6134685 (2000-10-01), Spano
patent: 6236223 (2001-05-01), Brady et al.
patent: 6782331 (2004-08-01), Ayadi
patent: 2002/0121915 (2002-09-01), Montull et al.
patent: 1 048 956 (2000-11-01), None

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